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1-1_SIM_MU
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*.bak
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--------------------------------------------------------------------------------
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--
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-- FileName: i2c_master.vhd
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-- Dependencies: none
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-- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version
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--
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-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
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-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
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-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
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-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
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-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
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-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
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-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
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-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
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--
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-- Version History
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-- Version 1.0 11/01/2012 Scott Larson
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-- Initial Public Release
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-- Version 2.0 06/20/2014 Scott Larson
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-- Added ability to interface with different slaves in the same transaction
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-- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error
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-- Corrected timing of when ack_error signal clears
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-- Version 2.1 10/21/2014 Scott Larson
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-- Replaced gated clock with clock enable
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-- Adjusted timing of SCL during start and stop conditions
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-- Version 2.2 02/05/2015 Scott Larson
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-- Corrected small SDA glitch introduced in version 2.1
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--
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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--USE ieee.std_logic_unsigned.all;
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ENTITY i2c_master IS
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GENERIC(
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input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz
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bus_clk : INTEGER := 400_000); --speed the i2c bus (scl) will run at in Hz
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PORT(
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clk : IN STD_LOGIC; --system clock
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reset_n : IN STD_LOGIC; --active low reset
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ena : IN STD_LOGIC; --latch in command
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addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
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rw : IN STD_LOGIC; --'0' is write, '1' is read
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data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
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busy : OUT STD_LOGIC; --indicates transaction in progress
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data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
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ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
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sda : INOUT STD_LOGIC; --serial data output of i2c bus
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scl : INOUT STD_LOGIC; --serial clock output of i2c bus
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scl_invert: IN STD_LOGIC --true if need to invert output SCL signal
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);
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END i2c_master;
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ARCHITECTURE logic OF i2c_master IS
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CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
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TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
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SIGNAL state : machine; --state machine
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SIGNAL data_clk : STD_LOGIC; --data clock for sda
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SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock
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SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl
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SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output
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SIGNAL sda_int : STD_LOGIC := '1'; --internal sda
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SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output
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SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write
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SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave
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SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave
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SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction
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SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl
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BEGIN
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--generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
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PROCESS(clk, reset_n)
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VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation
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BEGIN
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IF(reset_n = '0') THEN --reset asserted
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stretch <= '0';
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count := 0;
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ELSIF(clk'EVENT AND clk = '1') THEN
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data_clk_prev <= data_clk; --store previous value of data clock
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IF(count = divider*4-1) THEN --end of timing cycle
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count := 0; --reset timer
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ELSIF(stretch = '0') THEN --clock stretching from slave not detected
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count := count + 1; --continue clock generation timing
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END IF;
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CASE count IS
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WHEN 0 TO divider-1 => --first 1/4 cycle of clocking
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scl_clk <= '0';
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data_clk <= '0';
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WHEN divider TO divider*2-1 => --second 1/4 cycle of clocking
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scl_clk <= '0';
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data_clk <= '1';
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WHEN divider*2 TO divider*3-1 => --third 1/4 cycle of clocking
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scl_clk <= '1'; --release scl
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IF(scl = '0') THEN --detect if slave is stretching clock
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stretch <= '1';
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ELSE
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stretch <= '0';
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END IF;
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data_clk <= '1';
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WHEN OTHERS => --last 1/4 cycle of clocking
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scl_clk <= '1';
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data_clk <= '0';
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END CASE;
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END IF;
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END PROCESS;
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--state machine and writing to sda during scl low (data_clk rising edge)
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PROCESS(clk, reset_n)
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BEGIN
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IF(reset_n = '0') THEN --reset asserted
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state <= ready; --return to initial state
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busy <= '1'; --indicate not available
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scl_ena <= '0'; --sets scl high impedance
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sda_int <= '1'; --sets sda high impedance
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ack_error <= '0'; --clear acknowledge error flag
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bit_cnt <= 7; --restarts data bit counter
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data_rd <= "00000000"; --clear data read port
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ELSIF(clk'EVENT AND clk = '1') THEN
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IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge
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CASE state IS
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WHEN ready => --idle state
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IF(ena = '1') THEN --transaction requested
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busy <= '1'; --flag busy
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addr_rw <= addr & rw; --collect requested slave address and command
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data_tx <= data_wr; --collect requested data to write
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state <= start; --go to start bit
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ELSE --remain idle
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busy <= '0'; --unflag busy
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state <= ready; --remain idle
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END IF;
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WHEN start => --start bit of transaction
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busy <= '1'; --resume busy if continuous mode
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sda_int <= addr_rw(bit_cnt); --set first address bit to bus
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state <= command; --go to command
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WHEN command => --address and command byte of transaction
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IF(bit_cnt = 0) THEN --command transmit finished
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sda_int <= '1'; --release sda for slave acknowledge
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bit_cnt <= 7; --reset bit counter for "byte" states
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state <= slv_ack1; --go to slave acknowledge (command)
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ELSE --next clock cycle of command state
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bit_cnt <= bit_cnt - 1; --keep track of transaction bits
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sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus
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state <= command; --continue with command
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END IF;
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WHEN slv_ack1 => --slave acknowledge bit (command)
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IF(addr_rw(0) = '0') THEN --write command
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sda_int <= data_tx(bit_cnt); --write first bit of data
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state <= wr; --go to write byte
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ELSE --read command
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sda_int <= '1'; --release sda from incoming data
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state <= rd; --go to read byte
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END IF;
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WHEN wr => --write byte of transaction
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busy <= '1'; --resume busy if continuous mode
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IF(bit_cnt = 0) THEN --write byte transmit finished
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sda_int <= '1'; --release sda for slave acknowledge
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bit_cnt <= 7; --reset bit counter for "byte" states
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state <= slv_ack2; --go to slave acknowledge (write)
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ELSE --next clock cycle of write state
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bit_cnt <= bit_cnt - 1; --keep track of transaction bits
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sda_int <= data_tx(bit_cnt-1); --write next bit to bus
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state <= wr; --continue writing
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END IF;
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WHEN rd => --read byte of transaction
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busy <= '1'; --resume busy if continuous mode
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IF(bit_cnt = 0) THEN --read byte receive finished
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IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address
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sda_int <= '0'; --acknowledge the byte has been received
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ELSE --stopping or continuing with a write
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sda_int <= '1'; --send a no-acknowledge (before stop or repeated start)
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END IF;
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bit_cnt <= 7; --reset bit counter for "byte" states
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data_rd <= data_rx; --output received data
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state <= mstr_ack; --go to master acknowledge
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ELSE --next clock cycle of read state
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bit_cnt <= bit_cnt - 1; --keep track of transaction bits
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state <= rd; --continue reading
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END IF;
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WHEN slv_ack2 => --slave acknowledge bit (write)
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IF(ena = '1') THEN --continue transaction
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busy <= '0'; --continue is accepted
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addr_rw <= addr & rw; --collect requested slave address and command
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data_tx <= data_wr; --collect requested data to write
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IF(addr_rw = addr & rw) THEN --continue transaction with another write
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sda_int <= data_wr(bit_cnt); --write first bit of data
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state <= wr; --go to write byte
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ELSE --continue transaction with a read or new slave
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state <= start; --go to repeated start
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END IF;
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ELSE --complete transaction
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state <= stop; --go to stop bit
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END IF;
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WHEN mstr_ack => --master acknowledge bit after a read
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IF(ena = '1') THEN --continue transaction
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busy <= '0'; --continue is accepted and data received is available on bus
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addr_rw <= addr & rw; --collect requested slave address and command
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data_tx <= data_wr; --collect requested data to write
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IF(addr_rw = addr & rw) THEN --continue transaction with another read
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sda_int <= '1'; --release sda from incoming data
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state <= rd; --go to read byte
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ELSE --continue transaction with a write or new slave
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state <= start; --repeated start
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END IF;
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ELSE --complete transaction
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state <= stop; --go to stop bit
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END IF;
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WHEN stop => --stop bit of transaction
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busy <= '0'; --unflag busy
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state <= ready; --go to idle state
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END CASE;
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ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge
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CASE state IS
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WHEN start =>
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IF(scl_ena = '0') THEN --starting new transaction
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scl_ena <= '1'; --enable scl output
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ack_error <= '0'; --reset acknowledge error output
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END IF;
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WHEN slv_ack1 => --receiving slave acknowledge (command)
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IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
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ack_error <= '1'; --set error output if no-acknowledge
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END IF;
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WHEN rd => --receiving slave data
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data_rx(bit_cnt) <= sda; --receive current slave data bit
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WHEN slv_ack2 => --receiving slave acknowledge (write)
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IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
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ack_error <= '1'; --set error output if no-acknowledge
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END IF;
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WHEN stop =>
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scl_ena <= '0'; --disable scl
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WHEN OTHERS =>
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NULL;
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END CASE;
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END IF;
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END IF;
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END PROCESS;
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--set sda output
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WITH state SELECT
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sda_ena_n <= data_clk_prev WHEN start, --generate start condition
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NOT data_clk_prev WHEN stop, --generate stop condition
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sda_int WHEN OTHERS; --set to internal sda signal
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--set scl and sda outputs
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--scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z';
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scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0' AND scl_invert = '0') ELSE
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'1' WHEN (scl_ena = '1' AND scl_clk = '0' AND scl_invert = '1') ELSE
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'Z';
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sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z';
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END logic;
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@ -0,0 +1,301 @@
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------------------------------------------------------------
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-- File : I2C_slave.vhd
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------------------------------------------------------------
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-- Author : Peter Samarin <peter.samarin@gmail.com>
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------------------------------------------------------------
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-- Copyright (c) 2016 Peter Samarin
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------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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------------------------------------------------------------
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entity i2c_slave is
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generic (
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SLAVE_ADDR : std_logic_vector(6 downto 0));
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port (
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scl : inout std_logic;
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sda : inout std_logic;
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clk : in std_logic;
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rst : in std_logic;
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-- User interface
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read_req : out std_logic;
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data_to_master : in std_logic_vector(7 downto 0);
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data_valid : out std_logic;
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data_from_master : out std_logic_vector(7 downto 0));
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end entity i2c_slave;
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------------------------------------------------------------
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architecture arch of i2c_slave is
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-- this assumes that system's clock is much faster than SCL
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constant DEBOUNCING_WAIT_CYCLES : integer := 4;
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type state_t is (idle, get_address_and_cmd,
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answer_ack_start, write,
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read, read_ack_start,
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read_ack_got_rising, read_stop);
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-- I2C state management
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signal state_reg : state_t := idle;
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signal cmd_reg : std_logic := '0';
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signal bits_processed_reg : integer range 0 to 8 := 0;
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signal continue_reg : std_logic := '0';
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signal scl_reg : std_logic := '1';
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signal sda_reg : std_logic := '1';
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signal scl_debounced : std_logic := '1';
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signal sda_debounced : std_logic := '1';
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-- Helpers to figure out next state
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signal start_reg : std_logic := '0';
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signal stop_reg : std_logic := '0';
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signal scl_rising_reg : std_logic := '0';
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signal scl_falling_reg : std_logic := '0';
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|
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-- Address and data received from master
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signal addr_reg : std_logic_vector(6 downto 0) := (others => '0');
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signal data_reg : std_logic_vector(6 downto 0) := (others => '0');
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signal data_from_master_reg : std_logic_vector(7 downto 0) := (others => '0');
|
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signal scl_prev_reg : std_logic := '1';
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-- Slave writes on scl
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signal scl_wen_reg : std_logic := '0';
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signal scl_o_reg : std_logic := '0';
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signal sda_prev_reg : std_logic := '1';
|
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-- Slave writes on sda
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signal sda_wen_reg : std_logic := '0';
|
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signal sda_o_reg : std_logic := '0';
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-- User interface
|
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signal data_valid_reg : std_logic := '0';
|
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signal read_req_reg : std_logic := '0';
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signal data_to_master_reg : std_logic_vector(7 downto 0) := (others => '0');
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begin
|
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|
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-- debounce SCL and SDA
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SCL_debounce : entity work.debounce
|
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generic map (
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WAIT_CYCLES => DEBOUNCING_WAIT_CYCLES)
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port map (
|
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clk => clk,
|
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signal_in => scl_reg,
|
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signal_out => scl_debounced);
|
||||
|
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-- it might not make sense to debounce SDA, since master
|
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-- and slave can both write to it...
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SDA_debounce : entity work.debounce
|
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generic map (
|
||||
WAIT_CYCLES => DEBOUNCING_WAIT_CYCLES)
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port map (
|
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clk => clk,
|
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signal_in => sda_reg,
|
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signal_out => sda_debounced);
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|
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process (clk) is
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begin
|
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if rising_edge(clk) then
|
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-- save SCL in registers that are used for debouncing
|
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scl_reg <= scl;
|
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sda_reg <= sda;
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|
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-- Delay debounced SCL and SDA by 1 clock cycle
|
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scl_prev_reg <= scl_debounced;
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sda_prev_reg <= sda_debounced;
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-- Detect rising and falling SCL
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scl_rising_reg <= '0';
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if scl_prev_reg = '0' and scl_debounced = '1' then
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scl_rising_reg <= '1';
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end if;
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scl_falling_reg <= '0';
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if scl_prev_reg = '1' and scl_debounced = '0' then
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scl_falling_reg <= '1';
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||||
end if;
|
||||
|
||||
-- Detect I2C START condition
|
||||
start_reg <= '0';
|
||||
stop_reg <= '0';
|
||||
if scl_debounced = '1' and scl_prev_reg = '1' and
|
||||
sda_prev_reg = '1' and sda_debounced = '0' then
|
||||
start_reg <= '1';
|
||||
stop_reg <= '0';
|
||||
end if;
|
||||
|
||||
-- Detect I2C STOP condition
|
||||
if scl_prev_reg = '1' and scl_debounced = '1' and
|
||||
sda_prev_reg = '0' and sda_debounced = '1' then
|
||||
start_reg <= '0';
|
||||
stop_reg <= '1';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
----------------------------------------------------------
|
||||
-- I2C state machine
|
||||
----------------------------------------------------------
|
||||
process (clk) is
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
-- Default assignments
|
||||
sda_o_reg <= '0';
|
||||
sda_wen_reg <= '0';
|
||||
-- User interface
|
||||
data_valid_reg <= '0';
|
||||
read_req_reg <= '0';
|
||||
|
||||
case state_reg is
|
||||
|
||||
when idle =>
|
||||
if start_reg = '1' then
|
||||
state_reg <= get_address_and_cmd;
|
||||
bits_processed_reg <= 0;
|
||||
end if;
|
||||
|
||||
when get_address_and_cmd =>
|
||||
if scl_rising_reg = '1' then
|
||||
if bits_processed_reg < 7 then
|
||||
bits_processed_reg <= bits_processed_reg + 1;
|
||||
addr_reg(6-bits_processed_reg) <= sda_debounced;
|
||||
elsif bits_processed_reg = 7 then
|
||||
bits_processed_reg <= bits_processed_reg + 1;
|
||||
cmd_reg <= sda_debounced;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if bits_processed_reg = 8 and scl_falling_reg = '1' then
|
||||
bits_processed_reg <= 0;
|
||||
if addr_reg = SLAVE_ADDR then -- check req address
|
||||
state_reg <= answer_ack_start;
|
||||
if cmd_reg = '1' then -- issue read request
|
||||
read_req_reg <= '1';
|
||||
data_to_master_reg <= data_to_master;
|
||||
end if;
|
||||
else
|
||||
assert false
|
||||
report ("I2C: target/slave address mismatch (data is being sent to another slave).")
|
||||
severity note;
|
||||
state_reg <= idle;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
----------------------------------------------------
|
||||
-- I2C acknowledge to master
|
||||
----------------------------------------------------
|
||||
when answer_ack_start =>
|
||||
sda_wen_reg <= '1';
|
||||
sda_o_reg <= '0';
|
||||
if scl_falling_reg = '1' then
|
||||
if cmd_reg = '0' then
|
||||
state_reg <= write;
|
||||
else
|
||||
state_reg <= read;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
----------------------------------------------------
|
||||
-- WRITE
|
||||
----------------------------------------------------
|
||||
when write =>
|
||||
if scl_rising_reg = '1' then
|
||||
bits_processed_reg <= bits_processed_reg + 1;
|
||||
if bits_processed_reg < 7 then
|
||||
data_reg(6-bits_processed_reg) <= sda_debounced;
|
||||
else
|
||||
data_from_master_reg <= data_reg & sda_debounced;
|
||||
data_valid_reg <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if scl_falling_reg = '1' and bits_processed_reg = 8 then
|
||||
state_reg <= answer_ack_start;
|
||||
bits_processed_reg <= 0;
|
||||
end if;
|
||||
|
||||
----------------------------------------------------
|
||||
-- READ: send data to master
|
||||
----------------------------------------------------
|
||||
when read =>
|
||||
sda_wen_reg <= '1';
|
||||
sda_o_reg <= data_to_master_reg(7-bits_processed_reg);
|
||||
if scl_falling_reg = '1' then
|
||||
if bits_processed_reg < 7 then
|
||||
bits_processed_reg <= bits_processed_reg + 1;
|
||||
elsif bits_processed_reg = 7 then
|
||||
state_reg <= read_ack_start;
|
||||
bits_processed_reg <= 0;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
----------------------------------------------------
|
||||
-- I2C read master acknowledge
|
||||
----------------------------------------------------
|
||||
when read_ack_start =>
|
||||
if scl_rising_reg = '1' then
|
||||
state_reg <= read_ack_got_rising;
|
||||
if sda_debounced = '1' then -- nack = stop read
|
||||
continue_reg <= '0';
|
||||
else -- ack = continue read
|
||||
continue_reg <= '1';
|
||||
read_req_reg <= '1'; -- request reg byte
|
||||
data_to_master_reg <= data_to_master;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when read_ack_got_rising =>
|
||||
if scl_falling_reg = '1' then
|
||||
if continue_reg = '1' then
|
||||
if cmd_reg = '0' then
|
||||
state_reg <= write;
|
||||
else
|
||||
state_reg <= read;
|
||||
end if;
|
||||
else
|
||||
state_reg <= read_stop;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Wait for START or STOP to get out of this state
|
||||
when read_stop =>
|
||||
null;
|
||||
|
||||
-- Wait for START or STOP to get out of this state
|
||||
when others =>
|
||||
assert false
|
||||
report ("I2C: error: ended in an impossible state.")
|
||||
severity error;
|
||||
state_reg <= idle;
|
||||
end case;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Reset counter and state on start/stop
|
||||
--------------------------------------------------------
|
||||
if start_reg = '1' then
|
||||
state_reg <= get_address_and_cmd;
|
||||
bits_processed_reg <= 0;
|
||||
end if;
|
||||
|
||||
if stop_reg = '1' then
|
||||
state_reg <= idle;
|
||||
bits_processed_reg <= 0;
|
||||
end if;
|
||||
|
||||
if rst = '1' then
|
||||
state_reg <= idle;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
----------------------------------------------------------
|
||||
-- I2C interface
|
||||
----------------------------------------------------------
|
||||
sda <= sda_o_reg when sda_wen_reg = '1' else
|
||||
'Z';
|
||||
scl <= scl_o_reg when scl_wen_reg = '1' else
|
||||
'Z';
|
||||
----------------------------------------------------------
|
||||
-- User interface
|
||||
----------------------------------------------------------
|
||||
-- Master writes
|
||||
data_valid <= data_valid_reg;
|
||||
data_from_master <= data_from_master_reg;
|
||||
-- Master reads
|
||||
read_req <= read_req_reg;
|
||||
end architecture arch;
|
||||
|
|
@ -0,0 +1,358 @@
|
|||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use work.sim_switcher_pkg.all;
|
||||
|
||||
------------------------------------------------------------
|
||||
entity sim_mux is
|
||||
port (
|
||||
reg_sim_modemnum : arr_modnum_t(0 to 7);
|
||||
sim_rst_o : out std_logic_vector(7 downto 0);
|
||||
mod_simrst_i : in std_logic_vector(7 downto 0);
|
||||
sim_clk_o : out std_logic_vector(7 downto 0);
|
||||
mod_clk_i : in std_logic_vector(7 downto 0);
|
||||
mod_detect_o : out std_logic_vector(3 downto 0);
|
||||
sim_detect_i : in std_logic_vector(7 downto 0);
|
||||
sw_mod_data_i : out std_logic_vector(7 downto 0); -- For switched tri-state buffer there are input and output part of
|
||||
mod_data_i : in std_logic_vector(7 downto 0); -- the lines which are switched transparently, thus ports
|
||||
mod_data_o : out std_logic_vector(7 downto 0); -- sw_mod_data_i is actual output and sw_mod_data_o is
|
||||
sw_mod_data_o : in std_logic_vector(7 downto 0) -- actual input. Please, don't be confused.
|
||||
);
|
||||
end entity sim_mux;
|
||||
------------------------------------------------------------
|
||||
architecture arch of sim_mux is
|
||||
begin
|
||||
|
||||
-- Switch lines of SIM according to connected MODEM
|
||||
sim_rst_o(0) <= mod_simrst_i(0) when reg_sim_modemnum(0) = 0
|
||||
else mod_simrst_i(1) when reg_sim_modemnum(0) = 1
|
||||
else mod_simrst_i(2) when reg_sim_modemnum(0) = 2
|
||||
else mod_simrst_i(3) when reg_sim_modemnum(0) = 3
|
||||
else mod_simrst_i(4) when reg_sim_modemnum(0) = 4
|
||||
else mod_simrst_i(5) when reg_sim_modemnum(0) = 5
|
||||
else mod_simrst_i(6) when reg_sim_modemnum(0) = 6
|
||||
else mod_simrst_i(7) when reg_sim_modemnum(0) = 7
|
||||
else 'Z';
|
||||
sim_rst_o(1) <= mod_simrst_i(0) when reg_sim_modemnum(1) = 0
|
||||
else mod_simrst_i(1) when reg_sim_modemnum(1) = 1
|
||||
else mod_simrst_i(2) when reg_sim_modemnum(1) = 2
|
||||
else mod_simrst_i(3) when reg_sim_modemnum(1) = 3
|
||||
else mod_simrst_i(4) when reg_sim_modemnum(1) = 4
|
||||
else mod_simrst_i(5) when reg_sim_modemnum(1) = 5
|
||||
else mod_simrst_i(6) when reg_sim_modemnum(1) = 6
|
||||
else mod_simrst_i(7) when reg_sim_modemnum(1) = 7
|
||||
else 'Z';
|
||||
sim_rst_o(2) <= mod_simrst_i(0) when reg_sim_modemnum(2) = 0
|
||||
else mod_simrst_i(1) when reg_sim_modemnum(2) = 1
|
||||
else mod_simrst_i(2) when reg_sim_modemnum(2) = 2
|
||||
else mod_simrst_i(3) when reg_sim_modemnum(2) = 3
|
||||
else mod_simrst_i(4) when reg_sim_modemnum(2) = 4
|
||||
else mod_simrst_i(5) when reg_sim_modemnum(2) = 5
|
||||
else mod_simrst_i(6) when reg_sim_modemnum(2) = 6
|
||||
else mod_simrst_i(7) when reg_sim_modemnum(2) = 7
|
||||
else 'Z';
|
||||
sim_rst_o(3) <= mod_simrst_i(0) when reg_sim_modemnum(3) = 0
|
||||
else mod_simrst_i(1) when reg_sim_modemnum(3) = 1
|
||||
else mod_simrst_i(2) when reg_sim_modemnum(3) = 2
|
||||
else mod_simrst_i(3) when reg_sim_modemnum(3) = 3
|
||||
else mod_simrst_i(4) when reg_sim_modemnum(3) = 4
|
||||
else mod_simrst_i(5) when reg_sim_modemnum(3) = 5
|
||||
else mod_simrst_i(6) when reg_sim_modemnum(3) = 6
|
||||
else mod_simrst_i(7) when reg_sim_modemnum(3) = 7
|
||||
else 'Z';
|
||||
sim_rst_o(4) <= mod_simrst_i(0) when reg_sim_modemnum(4) = 0
|
||||
else mod_simrst_i(1) when reg_sim_modemnum(4) = 1
|
||||
else mod_simrst_i(2) when reg_sim_modemnum(4) = 2
|
||||
else mod_simrst_i(3) when reg_sim_modemnum(4) = 3
|
||||
else mod_simrst_i(4) when reg_sim_modemnum(4) = 4
|
||||
else mod_simrst_i(5) when reg_sim_modemnum(4) = 5
|
||||
else mod_simrst_i(6) when reg_sim_modemnum(4) = 6
|
||||
else mod_simrst_i(7) when reg_sim_modemnum(4) = 7
|
||||
else 'Z';
|
||||
sim_rst_o(5) <= mod_simrst_i(0) when reg_sim_modemnum(5) = 0
|
||||
else mod_simrst_i(1) when reg_sim_modemnum(5) = 1
|
||||
else mod_simrst_i(2) when reg_sim_modemnum(5) = 2
|
||||
else mod_simrst_i(3) when reg_sim_modemnum(5) = 3
|
||||
else mod_simrst_i(4) when reg_sim_modemnum(5) = 4
|
||||
else mod_simrst_i(5) when reg_sim_modemnum(5) = 5
|
||||
else mod_simrst_i(6) when reg_sim_modemnum(5) = 6
|
||||
else mod_simrst_i(7) when reg_sim_modemnum(5) = 7
|
||||
else 'Z';
|
||||
sim_rst_o(6) <= mod_simrst_i(0) when reg_sim_modemnum(6) = 0
|
||||
else mod_simrst_i(1) when reg_sim_modemnum(6) = 1
|
||||
else mod_simrst_i(2) when reg_sim_modemnum(6) = 2
|
||||
else mod_simrst_i(3) when reg_sim_modemnum(6) = 3
|
||||
else mod_simrst_i(4) when reg_sim_modemnum(6) = 4
|
||||
else mod_simrst_i(5) when reg_sim_modemnum(6) = 5
|
||||
else mod_simrst_i(6) when reg_sim_modemnum(6) = 6
|
||||
else mod_simrst_i(7) when reg_sim_modemnum(6) = 7
|
||||
else 'Z';
|
||||
sim_rst_o(7) <= mod_simrst_i(0) when reg_sim_modemnum(7) = 0
|
||||
else mod_simrst_i(1) when reg_sim_modemnum(7) = 1
|
||||
else mod_simrst_i(2) when reg_sim_modemnum(7) = 2
|
||||
else mod_simrst_i(3) when reg_sim_modemnum(7) = 3
|
||||
else mod_simrst_i(4) when reg_sim_modemnum(7) = 4
|
||||
else mod_simrst_i(5) when reg_sim_modemnum(7) = 5
|
||||
else mod_simrst_i(6) when reg_sim_modemnum(7) = 6
|
||||
else mod_simrst_i(7) when reg_sim_modemnum(7) = 7
|
||||
else 'Z';
|
||||
|
||||
-- Switch CLK line of SIM according to connected MODEM
|
||||
sim_clk_o(0) <= mod_clk_i(0) when reg_sim_modemnum(0) = 0
|
||||
else mod_clk_i(1) when reg_sim_modemnum(0) = 1
|
||||
else mod_clk_i(2) when reg_sim_modemnum(0) = 2
|
||||
else mod_clk_i(3) when reg_sim_modemnum(0) = 3
|
||||
else mod_clk_i(4) when reg_sim_modemnum(0) = 4
|
||||
else mod_clk_i(5) when reg_sim_modemnum(0) = 5
|
||||
else mod_clk_i(6) when reg_sim_modemnum(0) = 6
|
||||
else mod_clk_i(7) when reg_sim_modemnum(0) = 7
|
||||
else 'Z';
|
||||
sim_clk_o(1) <= mod_clk_i(0) when reg_sim_modemnum(1) = 0
|
||||
else mod_clk_i(1) when reg_sim_modemnum(1) = 1
|
||||
else mod_clk_i(2) when reg_sim_modemnum(1) = 2
|
||||
else mod_clk_i(3) when reg_sim_modemnum(1) = 3
|
||||
else mod_clk_i(4) when reg_sim_modemnum(1) = 4
|
||||
else mod_clk_i(5) when reg_sim_modemnum(1) = 5
|
||||
else mod_clk_i(6) when reg_sim_modemnum(1) = 6
|
||||
else mod_clk_i(7) when reg_sim_modemnum(1) = 7
|
||||
else 'Z';
|
||||
sim_clk_o(2) <= mod_clk_i(0) when reg_sim_modemnum(2) = 0
|
||||
else mod_clk_i(1) when reg_sim_modemnum(2) = 1
|
||||
else mod_clk_i(2) when reg_sim_modemnum(2) = 2
|
||||
else mod_clk_i(3) when reg_sim_modemnum(2) = 3
|
||||
else mod_clk_i(4) when reg_sim_modemnum(2) = 4
|
||||
else mod_clk_i(5) when reg_sim_modemnum(2) = 5
|
||||
else mod_clk_i(6) when reg_sim_modemnum(2) = 6
|
||||
else mod_clk_i(7) when reg_sim_modemnum(2) = 7
|
||||
else 'Z';
|
||||
sim_clk_o(3) <= mod_clk_i(0) when reg_sim_modemnum(3) = 0
|
||||
else mod_clk_i(1) when reg_sim_modemnum(3) = 1
|
||||
else mod_clk_i(2) when reg_sim_modemnum(3) = 2
|
||||
else mod_clk_i(3) when reg_sim_modemnum(3) = 3
|
||||
else mod_clk_i(4) when reg_sim_modemnum(3) = 4
|
||||
else mod_clk_i(5) when reg_sim_modemnum(3) = 5
|
||||
else mod_clk_i(6) when reg_sim_modemnum(3) = 6
|
||||
else mod_clk_i(7) when reg_sim_modemnum(3) = 7
|
||||
else 'Z';
|
||||
sim_clk_o(4) <= mod_clk_i(0) when reg_sim_modemnum(4) = 0
|
||||
else mod_clk_i(1) when reg_sim_modemnum(4) = 1
|
||||
else mod_clk_i(2) when reg_sim_modemnum(4) = 2
|
||||
else mod_clk_i(3) when reg_sim_modemnum(4) = 3
|
||||
else mod_clk_i(4) when reg_sim_modemnum(4) = 4
|
||||
else mod_clk_i(5) when reg_sim_modemnum(4) = 5
|
||||
else mod_clk_i(6) when reg_sim_modemnum(4) = 6
|
||||
else mod_clk_i(7) when reg_sim_modemnum(4) = 7
|
||||
else 'Z';
|
||||
sim_clk_o(5) <= mod_clk_i(0) when reg_sim_modemnum(5) = 0
|
||||
else mod_clk_i(1) when reg_sim_modemnum(5) = 1
|
||||
else mod_clk_i(2) when reg_sim_modemnum(5) = 2
|
||||
else mod_clk_i(3) when reg_sim_modemnum(5) = 3
|
||||
else mod_clk_i(4) when reg_sim_modemnum(5) = 4
|
||||
else mod_clk_i(5) when reg_sim_modemnum(5) = 5
|
||||
else mod_clk_i(6) when reg_sim_modemnum(5) = 6
|
||||
else mod_clk_i(7) when reg_sim_modemnum(5) = 7
|
||||
else 'Z';
|
||||
sim_clk_o(6) <= mod_clk_i(0) when reg_sim_modemnum(6) = 0
|
||||
else mod_clk_i(1) when reg_sim_modemnum(6) = 1
|
||||
else mod_clk_i(2) when reg_sim_modemnum(6) = 2
|
||||
else mod_clk_i(3) when reg_sim_modemnum(6) = 3
|
||||
else mod_clk_i(4) when reg_sim_modemnum(6) = 4
|
||||
else mod_clk_i(5) when reg_sim_modemnum(6) = 5
|
||||
else mod_clk_i(6) when reg_sim_modemnum(6) = 6
|
||||
else mod_clk_i(7) when reg_sim_modemnum(6) = 7
|
||||
else 'Z';
|
||||
sim_clk_o(7) <= mod_clk_i(0) when reg_sim_modemnum(7) = 0
|
||||
else mod_clk_i(1) when reg_sim_modemnum(7) = 1
|
||||
else mod_clk_i(2) when reg_sim_modemnum(7) = 2
|
||||
else mod_clk_i(3) when reg_sim_modemnum(7) = 3
|
||||
else mod_clk_i(4) when reg_sim_modemnum(7) = 4
|
||||
else mod_clk_i(5) when reg_sim_modemnum(7) = 5
|
||||
else mod_clk_i(6) when reg_sim_modemnum(7) = 6
|
||||
else mod_clk_i(7) when reg_sim_modemnum(7) = 7
|
||||
else 'Z';
|
||||
|
||||
-- Switch SIM DETECT line of SIM according to connected MODEM,
|
||||
mod_detect_o(0) <= sim_detect_i(0) when reg_sim_modemnum(0) = 0
|
||||
else sim_detect_i(1) when reg_sim_modemnum(1) = 0
|
||||
else sim_detect_i(2) when reg_sim_modemnum(2) = 0
|
||||
else sim_detect_i(3) when reg_sim_modemnum(3) = 0
|
||||
else sim_detect_i(4) when reg_sim_modemnum(4) = 0
|
||||
else sim_detect_i(5) when reg_sim_modemnum(5) = 0
|
||||
else sim_detect_i(6) when reg_sim_modemnum(6) = 0
|
||||
else sim_detect_i(7) when reg_sim_modemnum(7) = 0
|
||||
else 'Z';
|
||||
mod_detect_o(1) <= sim_detect_i(0) when reg_sim_modemnum(0) = 1
|
||||
else sim_detect_i(1) when reg_sim_modemnum(1) = 1
|
||||
else sim_detect_i(2) when reg_sim_modemnum(2) = 1
|
||||
else sim_detect_i(3) when reg_sim_modemnum(3) = 1
|
||||
else sim_detect_i(4) when reg_sim_modemnum(4) = 1
|
||||
else sim_detect_i(5) when reg_sim_modemnum(5) = 1
|
||||
else sim_detect_i(6) when reg_sim_modemnum(6) = 1
|
||||
else sim_detect_i(7) when reg_sim_modemnum(7) = 1
|
||||
else 'Z';
|
||||
mod_detect_o(2) <= sim_detect_i(0) when reg_sim_modemnum(0) = 2
|
||||
else sim_detect_i(1) when reg_sim_modemnum(1) = 2
|
||||
else sim_detect_i(2) when reg_sim_modemnum(2) = 2
|
||||
else sim_detect_i(3) when reg_sim_modemnum(3) = 2
|
||||
else sim_detect_i(4) when reg_sim_modemnum(4) = 2
|
||||
else sim_detect_i(5) when reg_sim_modemnum(5) = 2
|
||||
else sim_detect_i(6) when reg_sim_modemnum(6) = 2
|
||||
else sim_detect_i(7) when reg_sim_modemnum(7) = 2
|
||||
else 'Z';
|
||||
mod_detect_o(3) <= sim_detect_i(0) when reg_sim_modemnum(0) = 3
|
||||
else sim_detect_i(1) when reg_sim_modemnum(1) = 3
|
||||
else sim_detect_i(2) when reg_sim_modemnum(2) = 3
|
||||
else sim_detect_i(3) when reg_sim_modemnum(3) = 3
|
||||
else sim_detect_i(4) when reg_sim_modemnum(4) = 3
|
||||
else sim_detect_i(5) when reg_sim_modemnum(5) = 3
|
||||
else sim_detect_i(6) when reg_sim_modemnum(6) = 3
|
||||
else sim_detect_i(7) when reg_sim_modemnum(7) = 3
|
||||
else 'Z';
|
||||
|
||||
|
||||
sw_mod_data_i(0) <= mod_data_i(0) when reg_sim_modemnum(0) = 0
|
||||
else mod_data_i(1) when reg_sim_modemnum(0) = 1
|
||||
else mod_data_i(2) when reg_sim_modemnum(0) = 2
|
||||
else mod_data_i(3) when reg_sim_modemnum(0) = 3
|
||||
else mod_data_i(4) when reg_sim_modemnum(0) = 4
|
||||
else mod_data_i(5) when reg_sim_modemnum(0) = 5
|
||||
else mod_data_i(6) when reg_sim_modemnum(0) = 6
|
||||
else mod_data_i(7) when reg_sim_modemnum(0) = 7
|
||||
else '1';
|
||||
sw_mod_data_i(1) <= mod_data_i(0) when reg_sim_modemnum(1) = 0
|
||||
else mod_data_i(1) when reg_sim_modemnum(1) = 1
|
||||
else mod_data_i(2) when reg_sim_modemnum(1) = 2
|
||||
else mod_data_i(3) when reg_sim_modemnum(1) = 3
|
||||
else mod_data_i(4) when reg_sim_modemnum(1) = 4
|
||||
else mod_data_i(5) when reg_sim_modemnum(1) = 5
|
||||
else mod_data_i(6) when reg_sim_modemnum(1) = 6
|
||||
else mod_data_i(7) when reg_sim_modemnum(1) = 7
|
||||
else '1';
|
||||
sw_mod_data_i(2) <= mod_data_i(0) when reg_sim_modemnum(2) = 0
|
||||
else mod_data_i(1) when reg_sim_modemnum(2) = 1
|
||||
else mod_data_i(2) when reg_sim_modemnum(2) = 2
|
||||
else mod_data_i(3) when reg_sim_modemnum(2) = 3
|
||||
else mod_data_i(4) when reg_sim_modemnum(2) = 4
|
||||
else mod_data_i(5) when reg_sim_modemnum(2) = 5
|
||||
else mod_data_i(6) when reg_sim_modemnum(2) = 6
|
||||
else mod_data_i(7) when reg_sim_modemnum(2) = 7
|
||||
else '1';
|
||||
sw_mod_data_i(3) <= mod_data_i(0) when reg_sim_modemnum(3) = 0
|
||||
else mod_data_i(1) when reg_sim_modemnum(3) = 1
|
||||
else mod_data_i(2) when reg_sim_modemnum(3) = 2
|
||||
else mod_data_i(3) when reg_sim_modemnum(3) = 3
|
||||
else mod_data_i(4) when reg_sim_modemnum(3) = 4
|
||||
else mod_data_i(5) when reg_sim_modemnum(3) = 5
|
||||
else mod_data_i(6) when reg_sim_modemnum(3) = 6
|
||||
else mod_data_i(7) when reg_sim_modemnum(3) = 7
|
||||
else '1';
|
||||
sw_mod_data_i(4) <= mod_data_i(0) when reg_sim_modemnum(4) = 0
|
||||
else mod_data_i(1) when reg_sim_modemnum(4) = 1
|
||||
else mod_data_i(2) when reg_sim_modemnum(4) = 2
|
||||
else mod_data_i(3) when reg_sim_modemnum(4) = 3
|
||||
else mod_data_i(4) when reg_sim_modemnum(4) = 4
|
||||
else mod_data_i(5) when reg_sim_modemnum(4) = 5
|
||||
else mod_data_i(6) when reg_sim_modemnum(4) = 6
|
||||
else mod_data_i(7) when reg_sim_modemnum(4) = 7
|
||||
else '1';
|
||||
sw_mod_data_i(5) <= mod_data_i(0) when reg_sim_modemnum(5) = 0
|
||||
else mod_data_i(1) when reg_sim_modemnum(5) = 1
|
||||
else mod_data_i(2) when reg_sim_modemnum(5) = 2
|
||||
else mod_data_i(3) when reg_sim_modemnum(5) = 3
|
||||
else mod_data_i(4) when reg_sim_modemnum(5) = 4
|
||||
else mod_data_i(5) when reg_sim_modemnum(5) = 5
|
||||
else mod_data_i(6) when reg_sim_modemnum(5) = 6
|
||||
else mod_data_i(7) when reg_sim_modemnum(5) = 7
|
||||
else '1';
|
||||
sw_mod_data_i(6) <= mod_data_i(0) when reg_sim_modemnum(6) = 0
|
||||
else mod_data_i(1) when reg_sim_modemnum(6) = 1
|
||||
else mod_data_i(2) when reg_sim_modemnum(6) = 2
|
||||
else mod_data_i(3) when reg_sim_modemnum(6) = 3
|
||||
else mod_data_i(4) when reg_sim_modemnum(6) = 4
|
||||
else mod_data_i(5) when reg_sim_modemnum(6) = 5
|
||||
else mod_data_i(6) when reg_sim_modemnum(6) = 6
|
||||
else mod_data_i(7) when reg_sim_modemnum(6) = 7
|
||||
else '1';
|
||||
sw_mod_data_i(7) <= mod_data_i(0) when reg_sim_modemnum(7) = 0
|
||||
else mod_data_i(1) when reg_sim_modemnum(7) = 1
|
||||
else mod_data_i(2) when reg_sim_modemnum(7) = 2
|
||||
else mod_data_i(3) when reg_sim_modemnum(7) = 3
|
||||
else mod_data_i(4) when reg_sim_modemnum(7) = 4
|
||||
else mod_data_i(5) when reg_sim_modemnum(7) = 5
|
||||
else mod_data_i(6) when reg_sim_modemnum(7) = 6
|
||||
else mod_data_i(7) when reg_sim_modemnum(7) = 7
|
||||
else '1';
|
||||
|
||||
mod_data_o(0) <= sw_mod_data_o(0) when reg_sim_modemnum(0) = 0
|
||||
else sw_mod_data_o(1) when reg_sim_modemnum(1) = 0
|
||||
else sw_mod_data_o(2) when reg_sim_modemnum(2) = 0
|
||||
else sw_mod_data_o(3) when reg_sim_modemnum(3) = 0
|
||||
else sw_mod_data_o(4) when reg_sim_modemnum(4) = 0
|
||||
else sw_mod_data_o(5) when reg_sim_modemnum(5) = 0
|
||||
else sw_mod_data_o(6) when reg_sim_modemnum(6) = 0
|
||||
else sw_mod_data_o(7) when reg_sim_modemnum(7) = 0
|
||||
else 'Z';
|
||||
mod_data_o(1) <= sw_mod_data_o(0) when reg_sim_modemnum(0) = 1
|
||||
else sw_mod_data_o(1) when reg_sim_modemnum(1) = 1
|
||||
else sw_mod_data_o(2) when reg_sim_modemnum(2) = 1
|
||||
else sw_mod_data_o(3) when reg_sim_modemnum(3) = 1
|
||||
else sw_mod_data_o(4) when reg_sim_modemnum(4) = 1
|
||||
else sw_mod_data_o(5) when reg_sim_modemnum(5) = 1
|
||||
else sw_mod_data_o(6) when reg_sim_modemnum(6) = 1
|
||||
else sw_mod_data_o(7) when reg_sim_modemnum(7) = 1
|
||||
else 'Z';
|
||||
mod_data_o(2) <= sw_mod_data_o(0) when reg_sim_modemnum(0) = 2
|
||||
else sw_mod_data_o(1) when reg_sim_modemnum(1) = 2
|
||||
else sw_mod_data_o(2) when reg_sim_modemnum(2) = 2
|
||||
else sw_mod_data_o(3) when reg_sim_modemnum(3) = 2
|
||||
else sw_mod_data_o(4) when reg_sim_modemnum(4) = 2
|
||||
else sw_mod_data_o(5) when reg_sim_modemnum(5) = 2
|
||||
else sw_mod_data_o(6) when reg_sim_modemnum(6) = 2
|
||||
else sw_mod_data_o(7) when reg_sim_modemnum(7) = 2
|
||||
else 'Z';
|
||||
mod_data_o(3) <= sw_mod_data_o(0) when reg_sim_modemnum(0) = 3
|
||||
else sw_mod_data_o(1) when reg_sim_modemnum(1) = 3
|
||||
else sw_mod_data_o(2) when reg_sim_modemnum(2) = 3
|
||||
else sw_mod_data_o(3) when reg_sim_modemnum(3) = 3
|
||||
else sw_mod_data_o(4) when reg_sim_modemnum(4) = 3
|
||||
else sw_mod_data_o(5) when reg_sim_modemnum(5) = 3
|
||||
else sw_mod_data_o(6) when reg_sim_modemnum(6) = 3
|
||||
else sw_mod_data_o(7) when reg_sim_modemnum(7) = 3
|
||||
else 'Z';
|
||||
mod_data_o(4) <= sw_mod_data_o(0) when reg_sim_modemnum(0) = 4
|
||||
else sw_mod_data_o(1) when reg_sim_modemnum(1) = 4
|
||||
else sw_mod_data_o(2) when reg_sim_modemnum(2) = 4
|
||||
else sw_mod_data_o(3) when reg_sim_modemnum(3) = 4
|
||||
else sw_mod_data_o(4) when reg_sim_modemnum(4) = 4
|
||||
else sw_mod_data_o(5) when reg_sim_modemnum(5) = 4
|
||||
else sw_mod_data_o(6) when reg_sim_modemnum(6) = 4
|
||||
else sw_mod_data_o(7) when reg_sim_modemnum(7) = 4
|
||||
else 'Z';
|
||||
mod_data_o(5) <= sw_mod_data_o(0) when reg_sim_modemnum(0) = 5
|
||||
else sw_mod_data_o(1) when reg_sim_modemnum(1) = 5
|
||||
else sw_mod_data_o(2) when reg_sim_modemnum(2) = 5
|
||||
else sw_mod_data_o(3) when reg_sim_modemnum(3) = 5
|
||||
else sw_mod_data_o(4) when reg_sim_modemnum(4) = 5
|
||||
else sw_mod_data_o(5) when reg_sim_modemnum(5) = 5
|
||||
else sw_mod_data_o(6) when reg_sim_modemnum(6) = 5
|
||||
else sw_mod_data_o(7) when reg_sim_modemnum(7) = 5
|
||||
else 'Z';
|
||||
mod_data_o(6) <= sw_mod_data_o(0) when reg_sim_modemnum(0) = 6
|
||||
else sw_mod_data_o(1) when reg_sim_modemnum(1) = 6
|
||||
else sw_mod_data_o(2) when reg_sim_modemnum(2) = 6
|
||||
else sw_mod_data_o(3) when reg_sim_modemnum(3) = 6
|
||||
else sw_mod_data_o(4) when reg_sim_modemnum(4) = 6
|
||||
else sw_mod_data_o(5) when reg_sim_modemnum(5) = 6
|
||||
else sw_mod_data_o(6) when reg_sim_modemnum(6) = 6
|
||||
else sw_mod_data_o(7) when reg_sim_modemnum(7) = 6
|
||||
else 'Z';
|
||||
mod_data_o(7) <= sw_mod_data_o(0) when reg_sim_modemnum(0) = 7
|
||||
else sw_mod_data_o(1) when reg_sim_modemnum(1) = 7
|
||||
else sw_mod_data_o(2) when reg_sim_modemnum(2) = 7
|
||||
else sw_mod_data_o(3) when reg_sim_modemnum(3) = 7
|
||||
else sw_mod_data_o(4) when reg_sim_modemnum(4) = 7
|
||||
else sw_mod_data_o(5) when reg_sim_modemnum(5) = 7
|
||||
else sw_mod_data_o(6) when reg_sim_modemnum(6) = 7
|
||||
else sw_mod_data_o(7) when reg_sim_modemnum(7) = 7
|
||||
else 'Z';
|
||||
|
||||
end architecture arch;
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
package sim_switcher_pkg is
|
||||
|
||||
type arr_modnum_t is array (natural range <>) of natural range 0 to 15;
|
||||
|
||||
component sim_mux is
|
||||
port (
|
||||
reg_sim_modemnum : arr_modnum_t(0 to 7);
|
||||
sim_rst_o : out std_logic_vector(7 downto 0);
|
||||
mod_simrst_i : in std_logic_vector(7 downto 0);
|
||||
sim_clk_o : out std_logic_vector(7 downto 0);
|
||||
mod_clk_i : in std_logic_vector(7 downto 0);
|
||||
mod_detect_o : out std_logic_vector(3 downto 0);
|
||||
sim_detect_i : in std_logic_vector(7 downto 0);
|
||||
sw_mod_data_i : out std_logic_vector(7 downto 0); -- For switched tri-state buffer there are input and output part of
|
||||
mod_data_i : in std_logic_vector(7 downto 0); -- the lines which are switched transparently, thus ports
|
||||
mod_data_o : out std_logic_vector(7 downto 0); -- sw_mod_data_i is actual output and sw_mod_data_o is
|
||||
sw_mod_data_o : in std_logic_vector(7 downto 0) -- actual input. Please, don't be confused.
|
||||
);
|
||||
end component sim_mux;
|
||||
|
||||
component i2c_master IS
|
||||
generic (
|
||||
input_clk : integer := 50_000_000; --input clock speed from user logic in Hz
|
||||
bus_clk : integer := 400_000 --speed the i2c bus (scl) will run at in Hz
|
||||
);
|
||||
port (
|
||||
clk : in std_logic; --system clock
|
||||
reset_n : in std_logic; --active low reset
|
||||
ena : in std_logic; --latch in command
|
||||
addr : in std_logic_vector(6 downto 0); --address of target slave
|
||||
rw : in std_logic; --'0' is write, '1' is read
|
||||
data_wr : in std_logic_vector(7 downto 0); --data to write to slave
|
||||
busy : out std_logic; --indicates transaction in progress
|
||||
data_rd : out std_logic_vector(7 downto 0); --data read from slave
|
||||
ack_error : buffer std_logic; --flag if improper acknowledge from slave
|
||||
sda : inout std_logic; --serial data output of i2c bus
|
||||
scl : inout std_logic; --serial clock output of i2c bus
|
||||
scl_invert: in std_logic --true if need to invert output SCL signal
|
||||
);
|
||||
end component i2c_master;
|
||||
|
||||
component i2c_slave is
|
||||
generic (
|
||||
SLAVE_ADDR : std_logic_vector(6 downto 0)
|
||||
);
|
||||
port (
|
||||
scl : inout std_logic;
|
||||
sda : inout std_logic;
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
-- User interface
|
||||
read_req : out std_logic;
|
||||
data_to_master : in std_logic_vector(7 downto 0);
|
||||
data_valid : out std_logic;
|
||||
data_from_master : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component i2c_slave;
|
||||
|
||||
end package sim_switcher_pkg;
|
||||
File diff suppressed because it is too large
Load Diff
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Reference in New Issue