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Compiling, intermediate version with Part 1 changes for MBSr2, not tested

This commit is contained in:
matt 2020-07-22 21:49:19 +07:00
parent 49a8fd7224
commit 5cc12bdf6d
3 changed files with 434 additions and 106 deletions
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105
odio_repeater.vhd Normal file
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@ -0,0 +1,105 @@
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
------------------------------------------------------------
entity odio_repeater is
generic (
WAIT_CYCLES : integer := 3
);
port (
clk : in std_logic;
rstn : in std_logic;
signal_n1 : inout std_logic;
signal_n2 : inout std_logic
);
end entity odio_repeater;
------------------------------------------------------------
architecture arch of odio_repeater is
component debounce is
generic (
WAIT_CYCLES : integer := 5
);
port (
signal_in : in std_logic;
signal_out : out std_logic;
clk : in std_logic
);
end component;
type state_t is (idle, n1_to_n2, n2_to_n1);
signal state : state_t := idle;
signal s_n1_i_raw, s_n1_i, s_n1_o, s_n1_prev : std_logic;
signal s_n2_i_raw, s_n2_i, s_n2_o, s_n2_prev : std_logic;
begin
-- Tri-state IO handling
s_n1_i_raw <= signal_n1;
s_n2_i_raw <= signal_n2;
signal_n1 <= '0' when s_n1_o = '0' else 'Z';
signal_n2 <= '0' when s_n2_o = '0' else 'Z';
-- Debounce input lines
n1_debounce : debounce
generic map (
WAIT_CYCLES => WAIT_CYCLES
)
port map (
clk => clk,
signal_in => s_n1_i_raw,
signal_out => s_n1_i
);
n2_debounce : debounce
generic map (
WAIT_CYCLES => WAIT_CYCLES
)
port map (
clk => clk,
signal_in => s_n2_i_raw,
signal_out => s_n2_i
);
-- Main open-drain IO repeater process
rptr_proc: process(clk, rstn, s_n1_i, s_n2_i) is
begin
if rstn = '0' then
s_n1_o <= '1';
s_n2_o <= '1';
s_n1_prev <= s_n1_i;
s_n2_prev <= s_n2_i;
state <= idle;
elsif (rising_edge(clk)) then
s_n1_prev <= s_n1_i;
s_n2_prev <= s_n2_i;
case state is
when idle =>
if (s_n1_prev = '1' and s_n1_i = '0') then
s_n2_o <= '0';
state <= n1_to_n2;
elsif (s_n2_prev = '1' and s_n2_i = '0') then
s_n1_o <= '0';
state <= n2_to_n1;
end if;
when n1_to_n2 =>
if (s_n1_prev = '0' and s_n1_i = '1') then
s_n2_o <= '1';
state <= idle;
end if;
when n2_to_n1 =>
if (s_n2_prev = '0' and s_n2_i = '1') then
s_n1_o <= '1';
state <= idle;
end if;
end case;
end if;
end process;
end architecture arch;

12
sim_switcher_pkg.vhd
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@ -21,4 +21,16 @@ package sim_switcher_pkg is
);
end component i2c_slave;
component odio_repeater is
generic (
WAIT_CYCLES : integer := 3
);
port (
clk : in std_logic;
rstn : in std_logic;
signal_n1 : inout std_logic;
signal_n2 : inout std_logic
);
end component odio_repeater;
end package sim_switcher_pkg;

423
sim_switcher_top.vhd
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@ -35,7 +35,7 @@ entity sim_switcher_top is
i2c_sda_io : inout std_logic;
-- SIM board CONF bits
sim_board_conf_i :in std_logic_vector(2 downto 0);
sb_conf_i : in std_logic_vector(2 downto 0);
-- SIM signals
sim_detect_i : in std_logic_vector(7 downto 0);
@ -44,16 +44,47 @@ entity sim_switcher_top is
sim_clk_o : out std_logic_vector(7 downto 0);
sim_data_io : inout std_logic_vector(7 downto 0);
-- Virtual SIM signals
-- Virtual SIM data IO signals
vsim_data_io : inout std_logic_vector(3 downto 0);
-- Modem signals
-- Modem signals for SIM cards
mod_detect_o : out std_logic_vector(3 downto 0);
mod_wake_host_i : in std_logic_vector(3 downto 0);
mod_pwron_i : in std_logic_vector(7 downto 0);
mod_rst_i : in std_logic_vector(7 downto 0);
mod_simpwr_i : in std_logic_vector(7 downto 0);
mod_simrst_i : in std_logic_vector(7 downto 0);
mod_clk_i : in std_logic_vector(7 downto 0);
mod_data_io : inout std_logic_vector(7 downto 0)
mod_data_io : inout std_logic_vector(7 downto 0);
-- Modem LEDs
mod_led_o : out std_logic_vector(7 downto 0);
-- Modem manage signals
mod_pwr_o : out std_logic_vector(7 downto 0); -- Modem power on signals
mod_rstn_o : out std_logic_vector(7 downto 5); -- PCIe reset signal
mod_pciehstwake_i : in std_logic_vector(7 downto 5); -- PCIe wake host signal
-- Expansion card GPIO signals
exp_card_io : inout std_logic_vector(5 downto 0);
-- FAN power on signals
fan_o : out std_logic_vector(1 downto 0);
-- I2C slave interface FPGA-MCU (BitBang by MCU)
i2c_mcuscl_io : inout std_logic;
i2c_mcusda_io : inout std_logic;
-- POE IN add-in card
poe_in_vpres : in std_logic; -- Voltage present at card power output
poe_in_enn : out std_logic; -- PD enable signal (active low)
poe_in_t2p : in std_logic_vector(1 downto 0); -- PSE connected signal
-- POE OUT add-in card signals
pse_rst : out std_logic; -- PSE reset
pse_vpwr_enn : out std_logic; -- PSE enable (active low)
pse_i2c_scl_io : inout std_logic; -- PSE I2C SCL signal
pse_i2c_sda_io : inout std_logic; -- PSE I2C SDA signal
pse_intn : in std_logic; -- PSE interrupt (active low)
pse_vpwr_pg : in std_logic -- PSE power good signal
);
end entity sim_switcher_top;
@ -70,10 +101,11 @@ architecture rtl of sim_switcher_top is
);
end component;
constant FLASHES : natural := 5; -- Number of LED flashes on boot
constant CPU_RST_DURATION : natural := 100_000_000; -- 25_000_000 = 1sec
constant PON_RST_DURATION : natural := 10; -- 25_000_000 = 1sec
constant PON_CPU_DELAY_DURATION : natural := 75_000_000; -- 25_000_000 = 1sec
constant FLASHES : natural := 5; -- Number of LED flashes on boot
constant CPU_RST_DURATION : natural := 100_000_000; -- 25_000_000 = 1sec
constant PON_RST_DURATION : natural := 10; -- 25_000_000 = 1sec
constant PON_CPU_DELAY_DURATION : natural := 75_000_000; -- 25_000_000 = 1sec
constant SB_CONF_UPDATE_INTERVAL : natural := 25_000_000; -- 25_000_000 = 1sec
constant DEBOUNCING_WAIT_CYCLES : natural := 3; -- Number of debouncing wait cycles
@ -115,10 +147,40 @@ architecture rtl of sim_switcher_top is
signal s_mod_data_i, sdb_mod_data_i, sw_mod_data_i, sw_mod_data_prev, s_mod_data_o, sw_mod_data_o: std_logic_vector(7 downto 0);
-- SIM board CONF bits register
signal reg_sim_board_conf: std_logic_vector(2 downto 0);
signal reg_sim_board_conf : std_logic_vector(2 downto 0);
-- SIM switch IRQs for repeater state machine reset upon SIM change
signal reg_sim_change_irq: std_logic_vector(15 downto 0) := (others => '0');
signal reg_sim_change_irq : std_logic_vector(15 downto 0) := (others => '0');
-- Modem LED register
signal reg_mod_led : std_logic_vector(7 downto 0);
-- Modem power register
signal reg_mod_pwr : std_logic_vector(7 downto 0);
-- PCI-e signals
signal reg_pcie_rstn : std_logic_vector(7 downto 5);
signal reg_pcie_waken : std_logic_vector(7 downto 5);
-- M.2 modem wake host register
signal reg_mod_hstwake : std_logic_vector(3 downto 0);
-- FAN control register
signal reg_fan_ctl : std_logic_vector(1 downto 0);
-- PSE registers
signal reg_pse_status : std_logic_vector(1 downto 0);
signal reg_pse_ctl : std_logic_vector(1 downto 0);
-- POE PD registers
signal reg_poepd_status : std_logic_vector(2 downto 0);
signal reg_poepd_ctl : std_logic;
-- Expansion card IO tri-state control
signal reg_expio_line : std_logic_vector(5 downto 0);
signal reg_expio_output : std_logic_vector(5 downto 0);
signal s_exp_card_i : std_logic_vector(5 downto 0);
signal s_dbexp_card_i : std_logic_vector(5 downto 0);
-- State machine signals and types
type state_t is (idle, mod_to_sim, sim_to_mod);
@ -136,18 +198,69 @@ begin
reg_sim_det(7 downto 0) <= sim_detect_i;
reg_sim_det(15 downto 8) <= (others => '0');
-- reg_sim_modemnum <= (
-- 0 => 7,
-- 1 => 6,
-- 2 => 5,
-- 3 => 4,
-- 4 => 3,
-- 5 => 2,
-- 6 => 1,
-- 7 => 0
-- );
--reg_sim_change_irq <= (others => '0');
-- reg_sim_change_irq <= (others => '0');
mod_led_o <= reg_mod_led;
mod_pwr_o <= reg_mod_pwr;
mod_rstn_o <= reg_pcie_rstn;
reg_pcie_waken <= mod_pciehstwake_i;
reg_mod_hstwake <= mod_wake_host_i;
fan_o <= reg_fan_ctl;
-- PSE init
pse_rst <= reg_pse_ctl(0);
pse_vpwr_enn <= reg_pse_ctl(1);
reg_pse_status <= pse_intn&pse_vpwr_pg;
-- Connect PSE I2C bus to main I2C bus
pse_scl_rptr: odio_repeater
generic map (
WAIT_CYCLES => DEBOUNCING_WAIT_CYCLES
)
port map (
clk => clk25_i,
rstn => s_rstn_i,
signal_n1 => i2c_scl_io,
signal_n2 => pse_i2c_scl_io
);
pse_sda_rptr: odio_repeater
generic map (
WAIT_CYCLES => DEBOUNCING_WAIT_CYCLES
)
port map (
clk => clk25_i,
rstn => s_rstn_i,
signal_n1 => i2c_sda_io,
signal_n2 => pse_i2c_sda_io
);
-- POE PD init
reg_poepd_status <= poe_in_vpres&poe_in_t2p;
poe_in_enn <= reg_poepd_ctl;
-- Expansion card IO control
gen_expio_dbnc: for i in 0 to 5 generate
s_exp_card_i(i) <= exp_card_io(i);
exp_card_io(i) <= '0' when reg_expio_output(i) = '0' else 'Z';
reg_expio_line(i) <= s_dbexp_card_i(i);
expio_debounce : debounce
generic map (
WAIT_CYCLES => DEBOUNCING_WAIT_CYCLES
)
port map (
clk => clk25_i,
signal_in => s_exp_card_i(i),
signal_out => s_dbexp_card_i(i)
);
end generate gen_expio_dbnc;
---------------------------------------------------------
----------------------------------
-- Power-On FPGA IP-cores reset --
@ -247,10 +360,19 @@ begin
---------------------------
-- SIM board CONF update --
---------------------------
simb_conf_upd_proc: process(clk25_i) is
sb_conf_upd_proc: process(clk25_i, s_rstn_i, sb_conf_i) is
variable wait_cnt : natural := 0;
begin
if (rising_edge(clk25_i)) then
reg_sim_board_conf <= sim_board_conf_i;
if s_rstn_i = '0' then
wait_cnt := 0;
reg_sim_board_conf <= sb_conf_i;
elsif (rising_edge(clk25_i)) then
if (wait_cnt > SB_CONF_UPDATE_INTERVAL) then
wait_cnt := 0;
reg_sim_board_conf <= sb_conf_i;
else
wait_cnt := wait_cnt + 1;
end if;
end if;
end process;
@ -295,8 +417,15 @@ begin
reg_sim_change_irq <= (others => '0');
-- Turn on all SIM cards
reg_sim_pwr(7 downto 0) <= (others => '1');
reg_sim_pwr(15 downto 8) <= (others => '0');
reg_sim_pwr(7 downto 0) <= (others => '1'); -- Real SIMs power is on
reg_sim_pwr(15 downto 8) <= (others => '0'); -- Virtual SIMs power is "off"
reg_mod_led <= (others => '0'); -- Modem LEDs are not lit
reg_mod_pwr <= (others => '0'); -- Modem power is off
reg_pcie_rstn <= (others => '1'); -- PCIe RSTn is not active
reg_fan_ctl <= (others => '0'); -- FANs are off
reg_pse_ctl <= (others => '0'); -- POE out is on
reg_poepd_ctl <= '0'; -- POE PD enabled
reg_expio_output <= (others => '1'); -- All Expansion card IOs in HighZ at start
elsif (rising_edge(clk25_i)) then
case i2c_slv_state is
@ -320,6 +449,54 @@ begin
i2c_data_to_master <= "00000" & reg_sim_board_conf;
i2c_slv_state <= wait_while_sent;
when x"13" => -- Read FAN control regiser
i2c_data_to_master <= "000000" & reg_fan_ctl;
i2c_slv_state <= wait_while_sent;
when x"14" => -- Read POE OUT status register
i2c_data_to_master <= "000000" & reg_pse_status;
i2c_slv_state <= wait_while_sent;
when x"15" => -- Read POE OUT control register
i2c_data_to_master <= "000000" & reg_pse_ctl;
i2c_slv_state <= wait_while_sent;
when x"16" => -- Read POE IN status register
i2c_data_to_master <= "00000" & reg_poepd_status;
i2c_slv_state <= wait_while_sent;
when x"17" => -- Read POE IN control register
i2c_data_to_master <= "0000000" & reg_poepd_ctl;
i2c_slv_state <= wait_while_sent;
when x"18" => -- Read Expansion card IO lines
i2c_data_to_master <= "00" & reg_expio_line;
i2c_slv_state <= wait_while_sent;
when x"19" => -- Read Expansion card output register
i2c_data_to_master <= "00" & reg_expio_output;
i2c_slv_state <= wait_while_sent;
when x"05" => -- Read M.2 modem wake host register
i2c_data_to_master <= "0000"&reg_mod_hstwake(3 downto 0);
i2c_slv_state <= wait_while_sent;
when x"06" => -- Read modem LED register
i2c_data_to_master <= reg_mod_led(7 downto 0);
i2c_slv_state <= wait_while_sent;
when x"07" => -- Read modem power register
i2c_data_to_master <= reg_mod_pwr(7 downto 0);
i2c_slv_state <= wait_while_sent;
when x"08" => -- Read PCIe RSTn register
i2c_data_to_master <= reg_pcie_rstn(7 downto 5)&"00000";
i2c_slv_state <= wait_while_sent;
when x"09" => -- Read PCIe WAKEn register
i2c_data_to_master <= reg_pcie_waken(7 downto 5)&"00000";
i2c_slv_state <= wait_while_sent;
when x"0A" => -- Read SIMs detect register (LSB)
i2c_data_to_master <= reg_sim_det(7 downto 0);
i2c_slv_state <= wait_while_sent;
@ -358,11 +535,30 @@ begin
i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(7),4));
i2c_slv_state <= wait_while_sent;
when x"86" => -- Write modem LED register
i2c_slv_state <= receive_byte;
when x"87" => -- Write modem power register
i2c_slv_state <= receive_byte;
when x"88" => -- Write PCIe RSTn register
i2c_slv_state <= receive_byte;
when x"8C" => -- Write SIMs power register (LSB)
i2c_slv_state <= receive_byte;
-- when x"8D" => -- Write SIMs power register (MSB)
-- i2c_slv_state <= receive_byte;
when x"93" => -- Write FAN control regiser
i2c_slv_state <= receive_byte;
when x"95" => -- Write POE OUT control register
i2c_slv_state <= receive_byte;
when x"97" => -- Write POE IN control register
i2c_slv_state <= receive_byte;
when x"99" => -- Write Expansion card output register
i2c_slv_state <= receive_byte;
when x"A0" => -- Write SIM1 modem register
i2c_slv_state <= receive_byte;
when x"A1" => -- Write SIM2 modem register
@ -388,11 +584,30 @@ begin
when receive_byte =>
if (i2c_data_valid = '1') then
case s_reg_to_write is
when x"86" => -- Write modem LED register
reg_mod_led(7 downto 0) <= i2c_data_from_master(7 downto 0);
when x"87" => -- Write modem power register
reg_mod_pwr(7 downto 0) <= i2c_data_from_master(7 downto 0);
when x"88" => -- Write PCIe RSTn register
reg_pcie_rstn(7 downto 5) <= i2c_data_from_master(7 downto 5);
when x"8C" => -- Write SIMs power register (LSB)
reg_sim_pwr(7 downto 0) <= i2c_data_from_master(7 downto 0);
-- when x"8D" => -- Write SIMs power register (MSB)
-- reg_sim_pwr(15 downto 8) <= i2c_data_from_master(7 downto 0);
when x"93" => -- Write FAN control regiser
reg_fan_ctl(1 downto 0) <= i2c_data_from_master(1 downto 0);
when x"95" => -- Write POE OUT control register
reg_pse_ctl(1 downto 0) <= i2c_data_from_master(1 downto 0);
when x"97" => -- Write POE IN control register
reg_poepd_ctl <= i2c_data_from_master(0);
when x"99" => -- Write Expansion card output register
reg_expio_output <= i2c_data_from_master(5 downto 0);
when x"A0" => -- Write SIM1 modem register
reg_sim_modemnum(0) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
when x"A1" => -- Write SIM2 modem register
@ -446,77 +661,77 @@ begin
--- SIM card emulation test ---
-------------------------------
-- Switch RST line of SIM according to connected MODEM
sim_rst_o(0) <= mod_rst_i(0) when reg_sim_modemnum(0) = 0
else mod_rst_i(1) when reg_sim_modemnum(0) = 1
else mod_rst_i(2) when reg_sim_modemnum(0) = 2
else mod_rst_i(3) when reg_sim_modemnum(0) = 3
else mod_rst_i(4) when reg_sim_modemnum(0) = 4
else mod_rst_i(5) when reg_sim_modemnum(0) = 5
else mod_rst_i(6) when reg_sim_modemnum(0) = 6
else mod_rst_i(7) when reg_sim_modemnum(0) = 7
sim_rst_o(0) <= mod_simrst_i(0) when reg_sim_modemnum(0) = 0
else mod_simrst_i(1) when reg_sim_modemnum(0) = 1
else mod_simrst_i(2) when reg_sim_modemnum(0) = 2
else mod_simrst_i(3) when reg_sim_modemnum(0) = 3
else mod_simrst_i(4) when reg_sim_modemnum(0) = 4
else mod_simrst_i(5) when reg_sim_modemnum(0) = 5
else mod_simrst_i(6) when reg_sim_modemnum(0) = 6
else mod_simrst_i(7) when reg_sim_modemnum(0) = 7
else 'Z';
sim_rst_o(1) <= mod_rst_i(0) when reg_sim_modemnum(1) = 0
else mod_rst_i(1) when reg_sim_modemnum(1) = 1
else mod_rst_i(2) when reg_sim_modemnum(1) = 2
else mod_rst_i(3) when reg_sim_modemnum(1) = 3
else mod_rst_i(4) when reg_sim_modemnum(1) = 4
else mod_rst_i(5) when reg_sim_modemnum(1) = 5
else mod_rst_i(6) when reg_sim_modemnum(1) = 6
else mod_rst_i(7) when reg_sim_modemnum(1) = 7
sim_rst_o(1) <= mod_simrst_i(0) when reg_sim_modemnum(1) = 0
else mod_simrst_i(1) when reg_sim_modemnum(1) = 1
else mod_simrst_i(2) when reg_sim_modemnum(1) = 2
else mod_simrst_i(3) when reg_sim_modemnum(1) = 3
else mod_simrst_i(4) when reg_sim_modemnum(1) = 4
else mod_simrst_i(5) when reg_sim_modemnum(1) = 5
else mod_simrst_i(6) when reg_sim_modemnum(1) = 6
else mod_simrst_i(7) when reg_sim_modemnum(1) = 7
else 'Z';
sim_rst_o(2) <= mod_rst_i(0) when reg_sim_modemnum(2) = 0
else mod_rst_i(1) when reg_sim_modemnum(2) = 1
else mod_rst_i(2) when reg_sim_modemnum(2) = 2
else mod_rst_i(3) when reg_sim_modemnum(2) = 3
else mod_rst_i(4) when reg_sim_modemnum(2) = 4
else mod_rst_i(5) when reg_sim_modemnum(2) = 5
else mod_rst_i(6) when reg_sim_modemnum(2) = 6
else mod_rst_i(7) when reg_sim_modemnum(2) = 7
sim_rst_o(2) <= mod_simrst_i(0) when reg_sim_modemnum(2) = 0
else mod_simrst_i(1) when reg_sim_modemnum(2) = 1
else mod_simrst_i(2) when reg_sim_modemnum(2) = 2
else mod_simrst_i(3) when reg_sim_modemnum(2) = 3
else mod_simrst_i(4) when reg_sim_modemnum(2) = 4
else mod_simrst_i(5) when reg_sim_modemnum(2) = 5
else mod_simrst_i(6) when reg_sim_modemnum(2) = 6
else mod_simrst_i(7) when reg_sim_modemnum(2) = 7
else 'Z';
sim_rst_o(3) <= mod_rst_i(0) when reg_sim_modemnum(3) = 0
else mod_rst_i(1) when reg_sim_modemnum(3) = 1
else mod_rst_i(2) when reg_sim_modemnum(3) = 2
else mod_rst_i(3) when reg_sim_modemnum(3) = 3
else mod_rst_i(4) when reg_sim_modemnum(3) = 4
else mod_rst_i(5) when reg_sim_modemnum(3) = 5
else mod_rst_i(6) when reg_sim_modemnum(3) = 6
else mod_rst_i(7) when reg_sim_modemnum(3) = 7
sim_rst_o(3) <= mod_simrst_i(0) when reg_sim_modemnum(3) = 0
else mod_simrst_i(1) when reg_sim_modemnum(3) = 1
else mod_simrst_i(2) when reg_sim_modemnum(3) = 2
else mod_simrst_i(3) when reg_sim_modemnum(3) = 3
else mod_simrst_i(4) when reg_sim_modemnum(3) = 4
else mod_simrst_i(5) when reg_sim_modemnum(3) = 5
else mod_simrst_i(6) when reg_sim_modemnum(3) = 6
else mod_simrst_i(7) when reg_sim_modemnum(3) = 7
else 'Z';
sim_rst_o(4) <= mod_rst_i(0) when reg_sim_modemnum(4) = 0
else mod_rst_i(1) when reg_sim_modemnum(4) = 1
else mod_rst_i(2) when reg_sim_modemnum(4) = 2
else mod_rst_i(3) when reg_sim_modemnum(4) = 3
else mod_rst_i(4) when reg_sim_modemnum(4) = 4
else mod_rst_i(5) when reg_sim_modemnum(4) = 5
else mod_rst_i(6) when reg_sim_modemnum(4) = 6
else mod_rst_i(7) when reg_sim_modemnum(4) = 7
sim_rst_o(4) <= mod_simrst_i(0) when reg_sim_modemnum(4) = 0
else mod_simrst_i(1) when reg_sim_modemnum(4) = 1
else mod_simrst_i(2) when reg_sim_modemnum(4) = 2
else mod_simrst_i(3) when reg_sim_modemnum(4) = 3
else mod_simrst_i(4) when reg_sim_modemnum(4) = 4
else mod_simrst_i(5) when reg_sim_modemnum(4) = 5
else mod_simrst_i(6) when reg_sim_modemnum(4) = 6
else mod_simrst_i(7) when reg_sim_modemnum(4) = 7
else 'Z';
sim_rst_o(5) <= mod_rst_i(0) when reg_sim_modemnum(5) = 0
else mod_rst_i(1) when reg_sim_modemnum(5) = 1
else mod_rst_i(2) when reg_sim_modemnum(5) = 2
else mod_rst_i(3) when reg_sim_modemnum(5) = 3
else mod_rst_i(4) when reg_sim_modemnum(5) = 4
else mod_rst_i(5) when reg_sim_modemnum(5) = 5
else mod_rst_i(6) when reg_sim_modemnum(5) = 6
else mod_rst_i(7) when reg_sim_modemnum(5) = 7
sim_rst_o(5) <= mod_simrst_i(0) when reg_sim_modemnum(5) = 0
else mod_simrst_i(1) when reg_sim_modemnum(5) = 1
else mod_simrst_i(2) when reg_sim_modemnum(5) = 2
else mod_simrst_i(3) when reg_sim_modemnum(5) = 3
else mod_simrst_i(4) when reg_sim_modemnum(5) = 4
else mod_simrst_i(5) when reg_sim_modemnum(5) = 5
else mod_simrst_i(6) when reg_sim_modemnum(5) = 6
else mod_simrst_i(7) when reg_sim_modemnum(5) = 7
else 'Z';
sim_rst_o(6) <= mod_rst_i(0) when reg_sim_modemnum(6) = 0
else mod_rst_i(1) when reg_sim_modemnum(6) = 1
else mod_rst_i(2) when reg_sim_modemnum(6) = 2
else mod_rst_i(3) when reg_sim_modemnum(6) = 3
else mod_rst_i(4) when reg_sim_modemnum(6) = 4
else mod_rst_i(5) when reg_sim_modemnum(6) = 5
else mod_rst_i(6) when reg_sim_modemnum(6) = 6
else mod_rst_i(7) when reg_sim_modemnum(6) = 7
sim_rst_o(6) <= mod_simrst_i(0) when reg_sim_modemnum(6) = 0
else mod_simrst_i(1) when reg_sim_modemnum(6) = 1
else mod_simrst_i(2) when reg_sim_modemnum(6) = 2
else mod_simrst_i(3) when reg_sim_modemnum(6) = 3
else mod_simrst_i(4) when reg_sim_modemnum(6) = 4
else mod_simrst_i(5) when reg_sim_modemnum(6) = 5
else mod_simrst_i(6) when reg_sim_modemnum(6) = 6
else mod_simrst_i(7) when reg_sim_modemnum(6) = 7
else 'Z';
sim_rst_o(7) <= mod_rst_i(0) when reg_sim_modemnum(7) = 0
else mod_rst_i(1) when reg_sim_modemnum(7) = 1
else mod_rst_i(2) when reg_sim_modemnum(7) = 2
else mod_rst_i(3) when reg_sim_modemnum(7) = 3
else mod_rst_i(4) when reg_sim_modemnum(7) = 4
else mod_rst_i(5) when reg_sim_modemnum(7) = 5
else mod_rst_i(6) when reg_sim_modemnum(7) = 6
else mod_rst_i(7) when reg_sim_modemnum(7) = 7
sim_rst_o(7) <= mod_simrst_i(0) when reg_sim_modemnum(7) = 0
else mod_simrst_i(1) when reg_sim_modemnum(7) = 1
else mod_simrst_i(2) when reg_sim_modemnum(7) = 2
else mod_simrst_i(3) when reg_sim_modemnum(7) = 3
else mod_simrst_i(4) when reg_sim_modemnum(7) = 4
else mod_simrst_i(5) when reg_sim_modemnum(7) = 5
else mod_simrst_i(6) when reg_sim_modemnum(7) = 6
else mod_simrst_i(7) when reg_sim_modemnum(7) = 7
else 'Z';
-- Switch CLK line of SIM according to connected MODEM
@ -632,8 +847,7 @@ begin
else 'Z';
-- Route one-way signals from mod to SIM
sim_pwron_o <= reg_sim_pwr(7 downto 0);--(others => '1');--mod_pwron_i;
--mod_detect_o(3 downto 0) <= sim_detect_i(3 downto 0); --!! Switching
sim_pwron_o <= reg_sim_pwr(7 downto 0);
-- Bidir sinals routing
gen_datalines: for i in 0 to 7 generate
@ -643,9 +857,6 @@ begin
s_mod_data_i(i) <= mod_data_io(i);
mod_data_io(i) <= '0' when s_mod_data_o(i) = '0' else 'Z';
--sim_rst_o(i) <= mod_rst_i(i); --!! Switching
--sim_clk_o(i) <= mod_clk_i(i); --!! Switching
-- Debounce data lines
mod_dat_i_debounce : debounce
generic map (
@ -676,7 +887,7 @@ begin
else sdb_mod_data_i(5) when reg_sim_modemnum(0) = 5
else sdb_mod_data_i(6) when reg_sim_modemnum(0) = 6
else sdb_mod_data_i(7) when reg_sim_modemnum(0) = 7
else 'Z';
else '1';
sw_mod_data_i(1) <= sdb_mod_data_i(0) when reg_sim_modemnum(1) = 0
else sdb_mod_data_i(1) when reg_sim_modemnum(1) = 1
else sdb_mod_data_i(2) when reg_sim_modemnum(1) = 2
@ -685,7 +896,7 @@ begin
else sdb_mod_data_i(5) when reg_sim_modemnum(1) = 5
else sdb_mod_data_i(6) when reg_sim_modemnum(1) = 6
else sdb_mod_data_i(7) when reg_sim_modemnum(1) = 7
else 'Z';
else '1';
sw_mod_data_i(2) <= sdb_mod_data_i(0) when reg_sim_modemnum(2) = 0
else sdb_mod_data_i(1) when reg_sim_modemnum(2) = 1
else sdb_mod_data_i(2) when reg_sim_modemnum(2) = 2
@ -694,7 +905,7 @@ begin
else sdb_mod_data_i(5) when reg_sim_modemnum(2) = 5
else sdb_mod_data_i(6) when reg_sim_modemnum(2) = 6
else sdb_mod_data_i(7) when reg_sim_modemnum(2) = 7
else 'Z';
else '1';
sw_mod_data_i(3) <= sdb_mod_data_i(0) when reg_sim_modemnum(3) = 0
else sdb_mod_data_i(1) when reg_sim_modemnum(3) = 1
else sdb_mod_data_i(2) when reg_sim_modemnum(3) = 2
@ -703,7 +914,7 @@ begin
else sdb_mod_data_i(5) when reg_sim_modemnum(3) = 5
else sdb_mod_data_i(6) when reg_sim_modemnum(3) = 6
else sdb_mod_data_i(7) when reg_sim_modemnum(3) = 7
else 'Z';
else '1';
sw_mod_data_i(4) <= sdb_mod_data_i(0) when reg_sim_modemnum(4) = 0
else sdb_mod_data_i(1) when reg_sim_modemnum(4) = 1
else sdb_mod_data_i(2) when reg_sim_modemnum(4) = 2
@ -712,7 +923,7 @@ begin
else sdb_mod_data_i(5) when reg_sim_modemnum(4) = 5
else sdb_mod_data_i(6) when reg_sim_modemnum(4) = 6
else sdb_mod_data_i(7) when reg_sim_modemnum(4) = 7
else 'Z';
else '1';
sw_mod_data_i(5) <= sdb_mod_data_i(0) when reg_sim_modemnum(5) = 0
else sdb_mod_data_i(1) when reg_sim_modemnum(5) = 1
else sdb_mod_data_i(2) when reg_sim_modemnum(5) = 2
@ -721,7 +932,7 @@ begin
else sdb_mod_data_i(5) when reg_sim_modemnum(5) = 5
else sdb_mod_data_i(6) when reg_sim_modemnum(5) = 6
else sdb_mod_data_i(7) when reg_sim_modemnum(5) = 7
else 'Z';
else '1';
sw_mod_data_i(6) <= sdb_mod_data_i(0) when reg_sim_modemnum(6) = 0
else sdb_mod_data_i(1) when reg_sim_modemnum(6) = 1
else sdb_mod_data_i(2) when reg_sim_modemnum(6) = 2
@ -730,7 +941,7 @@ begin
else sdb_mod_data_i(5) when reg_sim_modemnum(6) = 5
else sdb_mod_data_i(6) when reg_sim_modemnum(6) = 6
else sdb_mod_data_i(7) when reg_sim_modemnum(6) = 7
else 'Z';
else '1';
sw_mod_data_i(7) <= sdb_mod_data_i(0) when reg_sim_modemnum(7) = 0
else sdb_mod_data_i(1) when reg_sim_modemnum(7) = 1
else sdb_mod_data_i(2) when reg_sim_modemnum(7) = 2
@ -739,7 +950,7 @@ begin
else sdb_mod_data_i(5) when reg_sim_modemnum(7) = 5
else sdb_mod_data_i(6) when reg_sim_modemnum(7) = 6
else sdb_mod_data_i(7) when reg_sim_modemnum(7) = 7
else 'Z';
else '1';
s_mod_data_o(0) <= sw_mod_data_o(0) when reg_sim_modemnum(0) = 0
else sw_mod_data_o(1) when reg_sim_modemnum(1) = 0