Removed commented code and unused module declaration
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matt
parent
7439984c8c
commit
58bb42cd13
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@ -60,30 +60,4 @@ package sim_switcher_pkg is
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);
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end component i2c_slave;
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component i2c_repeater is
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generic (
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WAIT_CYCLES : integer := 3
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);
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port (
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clk : in std_logic;
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rstn : in std_logic;
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pr_scl : inout std_logic;
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pr_sda : inout std_logic;
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sec_scl : inout std_logic;
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sec_sda : inout std_logic
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);
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end component i2c_repeater;
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component odio_repeater is
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generic (
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WAIT_CYCLES : integer := 3
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);
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port (
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clk : in std_logic;
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rstn : in std_logic;
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signal_n1 : inout std_logic;
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signal_n2 : inout std_logic
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);
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end component odio_repeater;
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end package sim_switcher_pkg;
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@ -8,10 +8,10 @@ use work.sim_switcher_pkg.all;
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entity sim_switcher_top is
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generic (
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-- General parameters
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SYSFREQ : integer := 25_000_000; -- System clock frequency
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INSIM : std_logic := '0'; -- In Simulation flag: 0 - real work (default), 1 - simulation
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SYSFREQ : integer := 25_000_000; -- System clock frequency
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INSIM : std_logic := '0'; -- In Simulation flag: 0 - real work (default), 1 - simulation
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-- I2C parameters
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I2C_SLAVE_ADDR : std_logic_vector(6 downto 0) := "1010111" -- Address of I2C slave, dafault 0x57
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I2C_SLAVE_ADDR : std_logic_vector(6 downto 0) := "1010111" -- Address of I2C slave, dafault 0x57
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);
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port (
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-- Clock and reset
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@ -33,7 +33,7 @@ entity sim_switcher_top is
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cpu_jtag_rstn_o : out std_logic;
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-- FPGA interrupt to CPU
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fpga_int_o : out std_logic; -- FPGA_INTn_V18, PIN_F12, active high
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fpga_int_o : out std_logic; -- FPGA_INTn_V18, PIN_F12, active high
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-- I2C slave interface
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i2c_scl_io : inout std_logic;
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@ -106,23 +106,23 @@ architecture rtl of sim_switcher_top is
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);
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end component;
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constant FLASHES : natural := 5; -- Number of LED flashes on boot
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constant CPU_RST_DURATION : natural := 100_000_000; -- 25_000_000 = 1sec
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constant PON_RST_DURATION : natural := 10; -- 25_000_000 = 1sec
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constant PON_CPU_DELAY_DURATION : natural := 75_000_000; -- 25_000_000 = 1sec
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constant SB_CONF_UPDATE_INTERVAL : natural := 25_000_000; -- 25_000_000 = 1sec
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constant FLASHES : natural := 5; -- Number of LED flashes on boot
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constant CPU_RST_DURATION : natural := 100_000_000; -- 25_000_000 = 1sec
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constant PON_RST_DURATION : natural := 10; -- 25_000_000 = 1sec
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constant PON_CPU_DELAY_DURATION : natural := 75_000_000; -- 25_000_000 = 1sec
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constant SB_CONF_UPDATE_INTERVAL : natural := 25_000_000; -- 25_000_000 = 1sec
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constant DEBOUNCING_WAIT_CYCLES : natural := 3; -- Number of debouncing wait cycles
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constant REPI2C_DEBOUNCING_WAIT_CYCLES : natural := 3; -- Number of debouncing wait cycles
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constant EXPIO_DEBOUNCING_WAIT_CYCLES : natural := 25; -- Number of debouncing wait cycles
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constant DEBOUNCING_WAIT_CYCLES : natural := 3; -- Number of debouncing wait cycles
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constant REPI2C_DEBOUNCING_WAIT_CYCLES : natural := 3; -- Number of debouncing wait cycles
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constant EXPIO_DEBOUNCING_WAIT_CYCLES : natural := 25; -- Number of debouncing wait cycles
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constant I2C_CLK : natural := 400_000; -- speed the i2c bus (scl) will run at in Hz
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constant I2C_CLK : natural := 400_000; -- speed the i2c bus (scl) will run at in Hz
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constant I2C_MAX_WAIT : natural := 2_500_000; -- 25_000_000 = 1sec
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constant I2C_MAX_WAIT : natural := 2_500_000; -- 25_000_000 = 1sec
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constant PSE_I2C_ADDR : std_logic_vector(6 downto 0) := "0100000"; -- 0x20
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constant PSE_REG_NUM : natural := 8;
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constant PSE_POLL_INTERVAL : natural := 25_000_000; -- 25_000_000 = 1sec
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constant PSE_POLL_INTERVAL : natural := 25_000_000; -- 25_000_000 = 1sec
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signal s_clk_i : std_logic; -- clock buffer
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signal s_rstn_i : std_logic; -- reset signal
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@ -272,6 +272,15 @@ begin
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-- Drive FAN control signals
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fan_o <= reg_fan_ctl;
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-- POE PD init
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reg_poepd_status(2) <= poe_in_vpres;
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reg_poepd_status(1 downto 0) <= poe_in_t2p(1 downto 0);
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poe_in_enn <= reg_poepd_ctl;
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----------------------
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-- Working with PSE --
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----------------------
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-- PSE init
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pse_rst <= reg_pse_ctl(0);
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pse_vpwr_enn <= reg_pse_ctl(1);
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@ -311,9 +320,8 @@ begin
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7 => x"14" -- R/W
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);
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------------------------------
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-- PSE read trigger process --
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------------------------------
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-- PSE read trigger process
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pse_readtrig_proc: process(clk25_i, s_rstn_i, wait_i2c_start, i2c_core_busy, pse_i2c_write_reg) is
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variable wait_cnt : natural := 0;
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begin
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@ -442,13 +450,13 @@ begin
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end if;
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when i2c_rd_wait =>
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if (s_i2c_busy_flag = '0') then -- Indicates data read in last command is ready
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pse_regs_value(reg_num_rd) <= s_i2c_data_rd; -- Store received byte
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if (s_i2c_busy_flag = '0') then -- Indicates data read in last command is ready
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pse_regs_value(reg_num_rd) <= s_i2c_data_rd; -- Store received byte
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reg_num_rd := reg_num_rd + 1;
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if (reg_num_rd = PSE_REG_NUM) then -- All regs are 1 byte length
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i2c_state <= wait_ack; -- Transaction complete, go to next state in design
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if (reg_num_rd = PSE_REG_NUM) then -- All regs are 1 byte length
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i2c_state <= wait_ack; -- Transaction complete, go to next state in design
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else
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i2c_state <= i2c_trn_start; -- Transaction complete, go to next state in design
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i2c_state <= i2c_trn_start; -- Transaction complete, go to next state in design
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end if;
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end if;
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@ -465,45 +473,9 @@ begin
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end if;
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end process pse_i2c_proc;
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-- pse_scl_rptr: odio_repeater
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-- generic map (
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-- WAIT_CYCLES => REPI2C_DEBOUNCING_WAIT_CYCLES
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-- )
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-- port map (
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-- clk => clk25_i,
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-- rstn => s_rstn_i,
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-- signal_n1 => i2c_scl_io,
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-- signal_n2 => pse_i2c_scl_io
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-- );
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-- pse_sda_rptr: odio_repeater
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-- generic map (
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-- WAIT_CYCLES => REPI2C_DEBOUNCING_WAIT_CYCLES
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-- )
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-- port map (
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-- clk => clk25_i,
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-- rstn => s_rstn_i,
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-- signal_n1 => i2c_sda_io,
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-- signal_n2 => pse_i2c_sda_io
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-- );
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-- pse_i2c_rptr: i2c_repeater
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-- generic map (
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-- WAIT_CYCLES => REPI2C_DEBOUNCING_WAIT_CYCLES
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-- )
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-- port map (
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-- clk => clk25_i,
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-- rstn => s_rstn_i,
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-- pr_scl => i2c_scl_io,
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-- pr_sda => i2c_sda_io,
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-- sec_scl => pse_i2c_scl_io,
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-- sec_sda => pse_i2c_sda_io
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-- );
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-- POE PD init
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reg_poepd_status(2) <= poe_in_vpres;
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reg_poepd_status(1 downto 0) <= poe_in_t2p(1 downto 0);
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poe_in_enn <= reg_poepd_ctl;
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------------------------------------
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-- Working woth expansion card IO --
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------------------------------------
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-- Expansion card IO control
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gen_expio_dbnc: for i in 0 to 5 generate
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@ -536,8 +508,6 @@ begin
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signal_out => sdb_pse_intn
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);
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----------------------------------------------
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--------------------------
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-- Interrupt generation --
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--------------------------
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