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Compiling, intermediate version for MBSr2, register renumber, interrupt generation, not tested

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matt 2020-07-30 00:08:03 +07:00
parent ef784c054e
commit aed7bf198a
1 changed files with 371 additions and 198 deletions
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569
sim_switcher_top.vhd
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@ -1,6 +1,8 @@
-- synthesis VHDL_INPUT_VERSION VHDL_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use work.sim_switcher_pkg.all;
entity sim_switcher_top is
@ -32,6 +34,7 @@ entity sim_switcher_top is
-- FPGA interrupt to CPU
fpga_int_o : out std_logic; -- FPGA_INTn_V18, PIN_F12, active high
-- I2C slave interface
i2c_scl_io : inout std_logic;
i2c_sda_io : inout std_logic;
@ -181,8 +184,26 @@ architecture rtl of sim_switcher_top is
-- Expansion card IO tri-state control
signal reg_expio_line : std_logic_vector(5 downto 0);
signal reg_expio_output : std_logic_vector(5 downto 0);
signal reg_expio_dir : std_logic_vector(5 downto 0);
signal reg_expio_intdirh2l : std_logic_vector(5 downto 0);
signal reg_expio_intdirl2h : std_logic_vector(5 downto 0);
signal reg_expio_intstatus : std_logic_vector(5 downto 0);
signal s_exp_card_i : std_logic_vector(5 downto 0);
signal s_dbexp_card_i : std_logic_vector(5 downto 0);
signal s_dbexp_card_prev : std_logic_vector(5 downto 0);
signal s_expio_intl2h : std_logic_vector(5 downto 0);
signal s_expio_inth2l : std_logic_vector(5 downto 0);
-- Interrupt related signals
signal reg_int_reason : std_logic_vector(7 downto 0);
signal s_int_reason_gpio : std_logic;
signal s_int_reason_reset : std_logic;
signal s_int_reason_reset_ack : std_logic;
signal s_int_expio_reset : std_logic;
signal s_int_expio_reset_ack : std_logic;
signal s_fpga_int_o : std_logic;
signal sdb_pse_intn : std_logic;
signal sdb_pse_intn_prev : std_logic;
-- State machine signals and types
type state_t is (idle, mod_to_sim, sim_to_mod);
@ -194,8 +215,8 @@ architecture rtl of sim_switcher_top is
begin
-- Interrupt generation
fpga_int_o <= not pse_intn;
-- Interrupt output routing
fpga_int_o <= s_fpga_int_o;
-- Currently unused SIM data lines for VirtualSIM
s_sim_data_i(15 downto 8) <= (others => '1');
@ -254,9 +275,11 @@ begin
-- Expansion card IO control
gen_expio_dbnc: for i in 0 to 5 generate
s_exp_card_i(i) <= exp_card_io(i);
exp_card_io(i) <= '0' when reg_expio_output(i) = '0' else 'Z';
reg_expio_line(i) <= s_dbexp_card_i(i);
s_exp_card_i(i) <= exp_card_io(i);
reg_expio_line(i) <= s_dbexp_card_i(i);
exp_card_io(i) <= '0' when reg_expio_output(i) = '0' and reg_expio_dir(i) = '1'
else '1' when reg_expio_output(i) = '1' and reg_expio_dir(i) = '1'
else 'Z';
expio_debounce : debounce
generic map (
@ -267,9 +290,78 @@ begin
signal_in => s_exp_card_i(i),
signal_out => s_dbexp_card_i(i)
);
end generate gen_expio_dbnc;
---------------------------------------------------------
pseint_debounce : debounce
generic map (
WAIT_CYCLES => DEBOUNCING_WAIT_CYCLES
)
port map (
clk => clk25_i,
signal_in => pse_intn,
signal_out => sdb_pse_intn
);
----------------------------------------------
--------------------------
-- Interrupt generation --
--------------------------
reg_expio_intstatus <= s_expio_intl2h or s_expio_inth2l;
int_gen_proc: process(clk25_i, s_rstn_i, sdb_pse_intn, sdb_pse_intn_prev, s_int_expio_reset, s_expio_intl2h, s_expio_inth2l, reg_expio_intdirl2h, reg_expio_intdirh2l, s_dbexp_card_i, s_dbexp_card_prev) is
begin
if s_rstn_i = '0' then
s_fpga_int_o <= '0';
s_expio_intl2h <= (others => '0');
s_expio_inth2l <= (others => '0');
reg_int_reason <= (others => '0');
elsif (rising_edge(clk25_i)) then
s_dbexp_card_prev <= s_dbexp_card_i;
sdb_pse_intn_prev <= sdb_pse_intn;
-- Catch IO line transitions for interrupt generating
for i in 0 to 5 loop
-- Generate Low-to-High IO transition interrupt
if (reg_expio_intdirl2h(i) = '1' and s_dbexp_card_prev(i) = '0' and s_dbexp_card_i(i) = '1') then
s_expio_intl2h(i) <= '1';
end if;
-- Generate High-to-Low IO transition interrupt
if (reg_expio_intdirh2l(i) = '1' and s_dbexp_card_prev(i) = '1' and s_dbexp_card_i(i) = '0') then
s_expio_inth2l(i) <= '1';
end if;
end loop;
-- Write the interrupt reason is IO bit
reg_int_reason(0) <= OR_REDUCE(s_expio_intl2h) or OR_REDUCE(s_expio_inth2l);
-- Write interrupt reason is PSE bit
if (sdb_pse_intn_prev = '1' and sdb_pse_intn = '0') then
reg_int_reason(1) <= '1';
end if;
if (s_int_expio_reset = '1') then
s_expio_intl2h <= (others => '0');
s_expio_inth2l <= (others => '0');
s_int_expio_reset_ack <= '1';
else
s_int_expio_reset_ack <= '0';
end if;
if (s_int_reason_reset = '1') then
reg_int_reason <= (others => '0');
s_int_reason_reset_ack <= '1';
else
s_int_reason_reset_ack <= '0';
end if;
s_fpga_int_o <= OR_REDUCE(s_expio_intl2h) or OR_REDUCE(s_expio_inth2l) or not sdb_pse_intn;
end if;
end process;
----------------------------------
-- Power-On FPGA IP-cores reset --
@ -434,235 +526,316 @@ begin
reg_fan_ctl <= (others => '0'); -- FANs are off
reg_pse_ctl <= (others => '0'); -- POE out is on
reg_poepd_ctl <= '0'; -- POE PD enabled
reg_expio_output <= (others => '1'); -- All Expansion card IOs in HighZ at start
reg_expio_output <= (others => '1'); -- All Expansion card IOs in HighZ at start
reg_expio_dir <= (others => '0'); -- All Expansion card IOs direction is IN
reg_expio_intdirh2l <= (others => '0'); -- Expansion card GPIO default line interrupt generation for High-to-Low transition is off
reg_expio_intdirl2h <= (others => '0'); -- Expansion card GPIO default line interrupt generation for Low-to-High transition is off
elsif (rising_edge(clk25_i)) then
case i2c_slv_state is
when ready =>
wait_cnt := 0;
i2c_data_to_master <= (others => '0');
if (i2c_data_valid = '1') then -- master sent a register addr byte
-- Save register address for later use in write procedure
s_reg_to_write <= i2c_data_from_master;
if (s_int_expio_reset_ack = '1') then
s_int_expio_reset <= '0';
end if;
case i2c_data_from_master is
when x"10" => -- Read ID byte
i2c_data_to_master <= x"18";
i2c_slv_state <= wait_while_sent;
if (s_int_reason_reset_ack = '1') then
s_int_reason_reset <= '0';
end if;
case i2c_slv_state is
when ready =>
wait_cnt := 0;
i2c_data_to_master <= (others => '0');
if (i2c_data_valid = '1') then -- master sent a register addr byte
-- Save register address for later use in write procedure
s_reg_to_write <= i2c_data_from_master;
when x"11" => -- Read SW Version byte (v1.0=0x18 MBCr1, v1.1=0x19 MBSr1, v2.0=0x28 MBSr2)
i2c_data_to_master <= x"28";
i2c_slv_state <= wait_while_sent;
case i2c_data_from_master is
when x"10" => -- Read ID byte
i2c_data_to_master <= x"18";
i2c_slv_state <= wait_while_sent;
when x"12" => -- Read SIM board model regiser
i2c_data_to_master <= "00000" & reg_sim_board_conf;
i2c_slv_state <= wait_while_sent;
when x"11" => -- Read SW Version byte (v1.0=0x18 MBCr1, v1.1=0x19 MBSr1, v2.0=0x28 MBSr2)
i2c_data_to_master <= x"28";
i2c_slv_state <= wait_while_sent;
when x"13" => -- Read FAN control regiser
i2c_data_to_master <= "000000" & reg_fan_ctl;
i2c_slv_state <= wait_while_sent;
when x"12" => -- Read SIM board model regiser
i2c_data_to_master <= "00000" & reg_sim_board_conf;
i2c_slv_state <= wait_while_sent;
when x"14" => -- Read POE OUT status register
i2c_data_to_master <= "000000" & reg_pse_status;
i2c_slv_state <= wait_while_sent;
when x"15" => -- Read interrupt reason register (autocleared on read)
i2c_data_to_master <= reg_int_reason;
s_int_reason_reset <= '1'; -- Clear reg on read
i2c_slv_state <= wait_while_sent;
when x"15" => -- Read POE OUT control register
i2c_data_to_master <= "000000" & reg_pse_ctl;
i2c_slv_state <= wait_while_sent;
when x"20" => -- Read SIM1 modem register
i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(0),4));
i2c_slv_state <= wait_while_sent;
when x"16" => -- Read POE IN status register
i2c_data_to_master <= "00000" & reg_poepd_status;
i2c_slv_state <= wait_while_sent;
when x"21" => -- Read SIM2 modem register
i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(1),4));
i2c_slv_state <= wait_while_sent;
when x"17" => -- Read POE IN control register
i2c_data_to_master <= "0000000" & reg_poepd_ctl;
i2c_slv_state <= wait_while_sent;
when x"22" => -- Read SIM3 modem register
i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(2),4));
i2c_slv_state <= wait_while_sent;
when x"18" => -- Read Expansion card IO lines
i2c_data_to_master <= "00" & reg_expio_line;
i2c_slv_state <= wait_while_sent;
when x"23" => -- Read SIM4 modem register
i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(3),4));
i2c_slv_state <= wait_while_sent;
when x"19" => -- Read Expansion card output register
i2c_data_to_master <= "00" & reg_expio_output;
i2c_slv_state <= wait_while_sent;
when x"24" => -- Read SIM5 modem register
i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(4),4));
i2c_slv_state <= wait_while_sent;
when x"05" => -- Read M.2 modem wake host register
i2c_data_to_master <= "0000"&reg_mod_hstwake(3 downto 0);
i2c_slv_state <= wait_while_sent;
when x"25" => -- Read SIM6 modem register
i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(5),4));
i2c_slv_state <= wait_while_sent;
when x"06" => -- Read modem LED register
i2c_data_to_master <= reg_mod_led(7 downto 0);
i2c_slv_state <= wait_while_sent;
when x"26" => -- Read SIM7 modem register
i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(6),4));
i2c_slv_state <= wait_while_sent;
when x"07" => -- Read modem power register
i2c_data_to_master <= reg_mod_pwr(7 downto 0);
i2c_slv_state <= wait_while_sent;
when x"08" => -- Read PCIe RSTn register
i2c_data_to_master <= reg_pcie_rstn(7 downto 5)&"00000";
i2c_slv_state <= wait_while_sent;
when x"27" => -- Read SIM8 modem register
i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(7),4));
i2c_slv_state <= wait_while_sent;
when x"09" => -- Read PCIe WAKEn register
i2c_data_to_master <= reg_pcie_waken(7 downto 5)&"00000";
i2c_slv_state <= wait_while_sent;
when x"35" => -- Read M.2 modem wake host register
i2c_data_to_master <= "0000"&reg_mod_hstwake(3 downto 0);
i2c_slv_state <= wait_while_sent;
when x"0A" => -- Read SIM detect register (LSB)
i2c_data_to_master <= reg_sim_det(7 downto 0);
i2c_slv_state <= wait_while_sent;
-- when x"0B" => -- Read SIM detect register (MSB)
-- i2c_data_to_master <= reg_sim_det(15 downto 8);
-- i2c_slv_state <= wait_while_sent;
when x"0C" => -- Read SIM power register (LSB)
i2c_data_to_master <= reg_sim_pwr(7 downto 0);
i2c_slv_state <= wait_while_sent;
-- when x"0D" => -- Read SIM power register (MSB)
-- i2c_data_to_master <= reg_sim_pwr(15 downto 8);
-- i2c_slv_state <= wait_while_sent;
when x"36" => -- Read modem LED register
i2c_data_to_master <= reg_mod_led(7 downto 0);
i2c_slv_state <= wait_while_sent;
when x"20" => -- Read SIM1 modem register
i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(0),4));
i2c_slv_state <= wait_while_sent;
when x"21" => -- Read SIM2 modem register
i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(1),4));
i2c_slv_state <= wait_while_sent;
when x"22" => -- Read SIM3 modem register
i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(2),4));
i2c_slv_state <= wait_while_sent;
when x"23" => -- Read SIM4 modem register
i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(3),4));
i2c_slv_state <= wait_while_sent;
when x"24" => -- Read SIM5 modem register
i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(4),4));
i2c_slv_state <= wait_while_sent;
when x"25" => -- Read SIM6 modem register
i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(5),4));
i2c_slv_state <= wait_while_sent;
when x"26" => -- Read SIM7 modem register
i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(6),4));
i2c_slv_state <= wait_while_sent;
when x"27" => -- Read SIM8 modem register
i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(7),4));
i2c_slv_state <= wait_while_sent;
when x"37" => -- Read modem power register
i2c_data_to_master <= reg_mod_pwr(7 downto 0);
i2c_slv_state <= wait_while_sent;
when x"86" => -- Write modem LED register
i2c_slv_state <= receive_byte;
when x"87" => -- Write modem power register
i2c_slv_state <= receive_byte;
when x"88" => -- Write PCIe RSTn register
i2c_slv_state <= receive_byte;
when x"38" => -- Read PCIe RSTn register
i2c_data_to_master <= reg_pcie_rstn(7 downto 5)&"00000";
i2c_slv_state <= wait_while_sent;
when x"8C" => -- Write SIMs power register (LSB)
i2c_slv_state <= receive_byte;
-- when x"8D" => -- Write SIMs power register (MSB)
-- i2c_slv_state <= receive_byte;
when x"39" => -- Read PCIe WAKEn register
i2c_data_to_master <= reg_pcie_waken(7 downto 5)&"00000";
i2c_slv_state <= wait_while_sent;
when x"93" => -- Write FAN control regiser
i2c_slv_state <= receive_byte;
when x"3A" => -- Read SIM detect register (LSB)
i2c_data_to_master <= reg_sim_det(7 downto 0);
i2c_slv_state <= wait_while_sent;
when x"95" => -- Write POE OUT control register
i2c_slv_state <= receive_byte;
-- when x"3B" => -- Read SIM detect register (MSB)
-- i2c_data_to_master <= reg_sim_det(15 downto 8);
-- i2c_slv_state <= wait_while_sent;
when x"97" => -- Write POE IN control register
i2c_slv_state <= receive_byte;
when x"3C" => -- Read SIM power register (LSB)
i2c_data_to_master <= reg_sim_pwr(7 downto 0);
i2c_slv_state <= wait_while_sent;
when x"99" => -- Write Expansion card output register
i2c_slv_state <= receive_byte;
-- when x"3D" => -- Read SIM power register (MSB)
-- i2c_data_to_master <= reg_sim_pwr(15 downto 8);
-- i2c_slv_state <= wait_while_sent;
when x"A0" => -- Write SIM1 modem register
i2c_slv_state <= receive_byte;
when x"A1" => -- Write SIM2 modem register
i2c_slv_state <= receive_byte;
when x"A2" => -- Write SIM3 modem register
i2c_slv_state <= receive_byte;
when x"A3" => -- Write SIM4 modem register
i2c_slv_state <= receive_byte;
when x"A4" => -- Write SIM5 modem register
i2c_slv_state <= receive_byte;
when x"A5" => -- Write SIM6 modem register
i2c_slv_state <= receive_byte;
when x"A6" => -- Write SIM7 modem register
i2c_slv_state <= receive_byte;
when x"A7" => -- Write SIM8 modem register
i2c_slv_state <= receive_byte;
when x"41" => -- Read Expansion card IO lines
i2c_data_to_master <= "00" & reg_expio_line;
i2c_slv_state <= wait_while_sent;
when others =>
i2c_slv_state <= ready;
end case;
end if;
when x"42" => -- Read Expansion card output value register
i2c_data_to_master <= "00" & reg_expio_output;
i2c_slv_state <= wait_while_sent;
when receive_byte =>
if (i2c_data_valid = '1') then
case s_reg_to_write is
when x"86" => -- Write modem LED register
reg_mod_led(7 downto 0) <= i2c_data_from_master(7 downto 0);
when x"87" => -- Write modem power register
reg_mod_pwr(7 downto 0) <= i2c_data_from_master(7 downto 0);
when x"88" => -- Write PCIe RSTn register
reg_pcie_rstn(7 downto 5) <= i2c_data_from_master(7 downto 5);
when x"43" => -- Read Expansion card direction (0 - IN, 1 - OUT) register
i2c_data_to_master <= "00" & reg_expio_dir;
i2c_slv_state <= wait_while_sent;
when x"8C" => -- Write SIMs power register (LSB)
reg_sim_pwr(7 downto 0) <= i2c_data_from_master(7 downto 0);
-- when x"8D" => -- Write SIMs power register (MSB)
-- reg_sim_pwr(15 downto 8) <= i2c_data_from_master(7 downto 0);
when x"44" => -- Read Expansion card GPIO interrupt generation for High-to-Low transition register
i2c_data_to_master <= "00" & reg_expio_intdirh2l;
i2c_slv_state <= wait_while_sent;
when x"93" => -- Write FAN control regiser
reg_fan_ctl(1 downto 0) <= i2c_data_from_master(1 downto 0);
when x"45" => -- Read Expansion card GPIO interrupt generation for Low-to-High transition register
i2c_data_to_master <= "00" & reg_expio_intdirl2h;
i2c_slv_state <= wait_while_sent;
when x"95" => -- Write POE OUT control register
reg_pse_ctl(1 downto 0) <= i2c_data_from_master(1 downto 0);
when x"46" => -- Read Expansion card GPIO interrupt status register (autocleared on read)
i2c_data_to_master <= "00" & reg_expio_intstatus;
s_int_expio_reset <= '1'; -- Clear reg on read
i2c_slv_state <= wait_while_sent;
when x"97" => -- Write POE IN control register
reg_poepd_ctl <= i2c_data_from_master(0);
when x"51" => -- Read FAN control regiser
i2c_data_to_master <= "000000" & reg_fan_ctl;
i2c_slv_state <= wait_while_sent;
when x"99" => -- Write Expansion card output register
reg_expio_output <= i2c_data_from_master(5 downto 0);
when x"52" => -- Read POE OUT status register
i2c_data_to_master <= "000000" & reg_pse_status;
i2c_slv_state <= wait_while_sent;
when x"A0" => -- Write SIM1 modem register
reg_sim_modemnum(0) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
when x"A1" => -- Write SIM2 modem register
reg_sim_modemnum(1) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
when x"A2" => -- Write SIM3 modem register
reg_sim_modemnum(2) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
when x"A3" => -- Write SIM4 modem register
reg_sim_modemnum(3) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
when x"A4" => -- Write SIM5 modem register
reg_sim_modemnum(4) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
when x"A5" => -- Write SIM6 modem register
reg_sim_modemnum(5) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
when x"A6" => -- Write SIM7 modem register
reg_sim_modemnum(6) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
when x"A7" => -- Write SIM8 modem register
reg_sim_modemnum(7) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
when x"53" => -- Read POE OUT control register
i2c_data_to_master <= "000000" & reg_pse_ctl;
i2c_slv_state <= wait_while_sent;
when others =>
null;
end case;
i2c_slv_state <= ready;
else
-- Wait timer to prevent freeze in waiting state
if (wait_cnt > I2C_MAX_WAIT) then
i2c_slv_state <= ready;
else
wait_cnt := wait_cnt + 1;
end if;
end if;
when x"54" => -- Read POE IN status register
i2c_data_to_master <= "00000" & reg_poepd_status;
i2c_slv_state <= wait_while_sent;
when wait_while_sent =>
if (i2c_read_req = '1') then
i2c_slv_state <= ready;
else
-- Wait timer to prevent freeze in waiting state
if (wait_cnt > I2C_MAX_WAIT) then
i2c_slv_state <= ready;
else
wait_cnt := wait_cnt + 1;
end if;
end if;
when x"55" => -- Read POE IN control register
i2c_data_to_master <= "0000000" & reg_poepd_ctl;
i2c_slv_state <= wait_while_sent;
when others =>
i2c_slv_state <= ready;
when x"A0" => -- Write SIM1 modem register
i2c_slv_state <= receive_byte;
end case;
when x"A1" => -- Write SIM2 modem register
i2c_slv_state <= receive_byte;
when x"A2" => -- Write SIM3 modem register
i2c_slv_state <= receive_byte;
when x"A3" => -- Write SIM4 modem register
i2c_slv_state <= receive_byte;
when x"A4" => -- Write SIM5 modem register
i2c_slv_state <= receive_byte;
when x"A5" => -- Write SIM6 modem register
i2c_slv_state <= receive_byte;
when x"A6" => -- Write SIM7 modem register
i2c_slv_state <= receive_byte;
when x"A7" => -- Write SIM8 modem register
i2c_slv_state <= receive_byte;
when x"B6" => -- Write modem LED register
i2c_slv_state <= receive_byte;
when x"B7" => -- Write modem power register
i2c_slv_state <= receive_byte;
when x"B8" => -- Write PCIe RSTn register
i2c_slv_state <= receive_byte;
when x"BC" => -- Write SIMs power register (LSB)
i2c_slv_state <= receive_byte;
-- when x"BD" => -- Write SIMs power register (MSB)
-- i2c_slv_state <= receive_byte;
when x"C2" => -- Write Expansion card output register
i2c_slv_state <= receive_byte;
when x"C3" => -- Write Expansion card direction register
i2c_slv_state <= receive_byte;
when x"C4" => -- Write Expansion card GPIO interrupt generation for High-to-Low transition register
i2c_slv_state <= receive_byte;
when x"C5" => -- Write Expansion card GPIO interrupt generation for Low-to-High transition register
i2c_slv_state <= receive_byte;
when x"D1" => -- Write FAN control regiser
i2c_slv_state <= receive_byte;
when x"D3" => -- Write POE OUT control register
i2c_slv_state <= receive_byte;
when x"D5" => -- Write POE IN control register
i2c_slv_state <= receive_byte;
when others =>
i2c_slv_state <= ready;
end case;
end if;
when receive_byte =>
if (i2c_data_valid = '1') then
case s_reg_to_write is
when x"A0" => -- Write SIM1 modem register
reg_sim_modemnum(0) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
when x"A1" => -- Write SIM2 modem register
reg_sim_modemnum(1) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
when x"A2" => -- Write SIM3 modem register
reg_sim_modemnum(2) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
when x"A3" => -- Write SIM4 modem register
reg_sim_modemnum(3) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
when x"A4" => -- Write SIM5 modem register
reg_sim_modemnum(4) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
when x"A5" => -- Write SIM6 modem register
reg_sim_modemnum(5) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
when x"A6" => -- Write SIM7 modem register
reg_sim_modemnum(6) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
when x"A7" => -- Write SIM8 modem register
reg_sim_modemnum(7) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
when x"B6" => -- Write modem LED register
reg_mod_led(7 downto 0) <= i2c_data_from_master(7 downto 0);
when x"B7" => -- Write modem power register
reg_mod_pwr(7 downto 0) <= i2c_data_from_master(7 downto 0);
when x"B8" => -- Write PCIe RSTn register
reg_pcie_rstn(7 downto 5) <= i2c_data_from_master(7 downto 5);
when x"BC" => -- Write SIMs power register (LSB)
reg_sim_pwr(7 downto 0) <= i2c_data_from_master(7 downto 0);
-- when x"BD" => -- Write SIMs power register (MSB)
-- reg_sim_pwr(15 downto 8) <= i2c_data_from_master(7 downto 0);
when x"C2" => -- Write Expansion card output register
reg_expio_output <= i2c_data_from_master(5 downto 0);
when x"C3" => -- Write Expansion card direction register
reg_expio_dir <= i2c_data_from_master(5 downto 0);
when x"C4" => -- Write Expansion card GPIO interrupt generation for High-to-Low transition register
reg_expio_intdirh2l <= i2c_data_from_master(5 downto 0);
when x"C5" => -- Write Expansion card GPIO interrupt generation for Low-to-High transition register
reg_expio_intdirl2h <= i2c_data_from_master(5 downto 0);
when x"D1" => -- Write FAN control regiser
reg_fan_ctl(1 downto 0) <= i2c_data_from_master(1 downto 0);
when x"D3" => -- Write POE OUT control register
reg_pse_ctl(1 downto 0) <= i2c_data_from_master(1 downto 0);
when x"D5" => -- Write POE IN control register
reg_poepd_ctl <= i2c_data_from_master(0);
when others =>
null;
end case;
i2c_slv_state <= ready;
else
-- Wait timer to prevent freeze in waiting state
if (wait_cnt > I2C_MAX_WAIT) then
i2c_slv_state <= ready;
else
wait_cnt := wait_cnt + 1;
end if;
end if;
when wait_while_sent =>
if (i2c_read_req = '1') then
i2c_slv_state <= ready;
else
-- Wait timer to prevent freeze in waiting state
if (wait_cnt > I2C_MAX_WAIT) then
i2c_slv_state <= ready;
else
wait_cnt := wait_cnt + 1;
end if;
end if;
when others =>
i2c_slv_state <= ready;
end case;
end if;
end process i2c_slv_process;