Working muxing with I2C slave interface. TO DO: protection from SIM attach to several modems
This commit is contained in:
matt
parent
86c7da5075
commit
d82a0ab464
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@ -30,6 +30,10 @@ entity sim_switcher_top is
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cpu_trstn_o : out std_logic;
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cpu_jtag_rstn_o : out std_logic;
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-- I2C slave interface
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i2c_scl_io : inout std_logic;
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i2c_sda_io : inout std_logic;
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-- SIM signals
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sim_detect_i : in std_logic_vector(7 downto 0);
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sim_pwron_o : out std_logic_vector(7 downto 0);
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@ -69,7 +73,9 @@ architecture rtl of sim_switcher_top is
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constant PON_CPU_DELAY_DURATION : natural := 75_000_000; -- 25_000_000 = 1sec
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constant DEBOUNCING_WAIT_CYCLES : natural := 3; -- Number of debouncing wait cycles
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constant I2C_MAX_WAIT : natural := 2_500_000; -- 25_000_000 = 1sec
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signal s_clk_i : std_logic; -- clock buffer
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signal s_rstn_i : std_logic; -- reset signal
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signal s_rst_i : std_logic; -- reset signal
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@ -95,10 +101,9 @@ architecture rtl of sim_switcher_top is
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type i2c_fsm_t is (ready, receive_byte, wait_while_sent);
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signal i2c_slv_state : i2c_fsm_t := ready;
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-- signal reg_sim_sel : sim_mux_addr_t(3 downto 0);
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-- signal reg_sim_pwr : std_logic_vector(15 downto 0);
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-- signal reg_sim_det : std_logic_vector(15 downto 0);
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-- signal s_reg_to_write : std_logic_vector(7 downto 0);
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signal reg_sim_pwr : std_logic_vector(15 downto 0);
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signal reg_sim_det : std_logic_vector(15 downto 0);
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signal s_reg_to_write : std_logic_vector(7 downto 0);
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-- SIM data signals
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signal s_sim_data_i, sdb_sim_data_i, sdb_sim_data_prev, s_sim_data_o: std_logic_vector(15 downto 0);
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@ -122,18 +127,21 @@ begin
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s_sim_data_i(15 downto 8) <= (others => '1');
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sdb_sim_data_i(15 downto 8) <= (others => '1');
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reg_sim_modemnum <= (
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0 => 7,
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1 => 6,
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2 => 5,
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3 => 4,
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4 => 3,
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5 => 2,
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6 => 1,
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7 => 0
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);
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reg_sim_det(7 downto 0) <= sim_detect_i;
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reg_sim_det(15 downto 8) <= (others => '0');
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reg_sim_change_irq <= (others => '0');
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-- reg_sim_modemnum <= (
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-- 0 => 7,
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-- 1 => 6,
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-- 2 => 5,
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-- 3 => 4,
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-- 4 => 3,
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-- 5 => 2,
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-- 6 => 1,
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-- 7 => 0
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-- );
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-- reg_sim_change_irq <= (others => '0');
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----------------------------------
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-- Power-On FPGA IP-cores reset --
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@ -233,159 +241,185 @@ begin
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--------------------------------
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-- I2C slave interface to CPU --
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--------------------------------
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-- inst_i2c_slave: i2c_slave
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-- generic map (
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-- SLAVE_ADDR => I2C_SLAVE_ADDR
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-- )
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-- port map(
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-- scl => i2c_scl_io,
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-- sda => i2c_sda_io,
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-- clk => clk25_i,
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-- rst => s_rst_i,
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-- read_req => i2c_read_req,
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-- data_to_master => i2c_data_to_master,
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-- data_valid => i2c_data_valid,
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-- data_from_master => i2c_data_from_master
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-- );
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inst_i2c_slave: i2c_slave
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generic map (
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SLAVE_ADDR => I2C_SLAVE_ADDR
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)
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port map(
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scl => i2c_scl_io,
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sda => i2c_sda_io,
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clk => clk25_i,
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rst => s_rst_i,
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read_req => i2c_read_req,
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data_to_master => i2c_data_to_master,
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data_valid => i2c_data_valid,
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data_from_master => i2c_data_from_master
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);
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-- i2c_slv_process : process (clk25_i, s_rstn_i)
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-- variable wait_cnt : natural := 0;
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-- begin
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-- if (s_rstn_i = '0') then
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-- i2c_data_to_master <= (others => '0');
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-- wait_cnt := 0;
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i2c_slv_process : process (clk25_i, s_rstn_i)
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variable wait_cnt : natural := 0;
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begin
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if (s_rstn_i = '0') then
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i2c_data_to_master <= (others => '0');
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wait_cnt := 0;
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-- -- SIM select reset: default is SIM#1
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-- reg_sim_sel <= (others => (others => '0'));
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-- SIM attach reset assigment: default is 1-to-1 SIM to MODEM connection
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reg_sim_modemnum <= (
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0 => 0,
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1 => 1,
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2 => 2,
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3 => 3,
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4 => 4,
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5 => 5,
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6 => 6,
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7 => 7
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);
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-- SIM change IRQ register reset
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reg_sim_change_irq <= (others => '0');
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-- -- Turn on all SIM cards
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-- reg_sim_pwr <= (others => '1');
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-- Turn on all SIM cards
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reg_sim_pwr(7 downto 0) <= (others => '1');
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reg_sim_pwr(15 downto 8) <= (others => '0');
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-- -- Only first SIMs are powered on upon reset
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-- -- reg_sim_pwr(0) <= '1';
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-- -- reg_sim_pwr(3 downto 1) <= (others => '0');
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-- --
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-- -- reg_sim_pwr(4) <= '1';
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-- -- reg_sim_pwr(7 downto 5) <= (others => '0');
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-- --
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-- -- reg_sim_pwr(8) <= '1';
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-- -- reg_sim_pwr(11 downto 9) <= (others => '0');
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-- --
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-- -- reg_sim_pwr(12) <= '1';
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-- -- reg_sim_pwr(15 downto 13) <= (others => '0');
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--
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-- reg_sim_change_irq <= (others => '0');
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--
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-- elsif (rising_edge(clk25_i)) then
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-- case i2c_slv_state is
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-- when ready =>
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-- wait_cnt := 0;
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-- i2c_data_to_master <= (others => '0');
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-- if (i2c_data_valid = '1') then -- master sent a register addr byte
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-- -- Save register address for later use in write procedure
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-- s_reg_to_write <= i2c_data_from_master;
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elsif (rising_edge(clk25_i)) then
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case i2c_slv_state is
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when ready =>
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wait_cnt := 0;
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i2c_data_to_master <= (others => '0');
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if (i2c_data_valid = '1') then -- master sent a register addr byte
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-- Save register address for later use in write procedure
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s_reg_to_write <= i2c_data_from_master;
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-- case i2c_data_from_master is
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-- when x"10" => -- Read ID byte
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-- i2c_data_to_master <= x"18";
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-- i2c_slv_state <= wait_while_sent;
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case i2c_data_from_master is
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when x"10" => -- Read ID byte
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i2c_data_to_master <= x"18";
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i2c_slv_state <= wait_while_sent;
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-- when x"11" => -- Read SW Version byte (v1.0=0x18, v1.1=0x19)
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-- i2c_data_to_master <= x"19";
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-- i2c_slv_state <= wait_while_sent;
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when x"11" => -- Read SW Version byte (v1.0=0x18, v1.1=0x19, v2.0=0x28)
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i2c_data_to_master <= x"20";
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i2c_slv_state <= wait_while_sent;
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-- when x"0A" => -- Read SIMs detect register (LSB)
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-- i2c_data_to_master <= reg_sim_det(7 downto 0);
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-- i2c_slv_state <= wait_while_sent;
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-- when x"0B" => -- Read SIMs detect register (MSB)
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-- i2c_data_to_master <= reg_sim_det(15 downto 8);
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-- i2c_slv_state <= wait_while_sent;
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-- when x"0C" => -- Read SIMs power register (LSB)
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-- i2c_data_to_master <= reg_sim_pwr(7 downto 0);
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-- i2c_slv_state <= wait_while_sent;
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-- when x"0D" => -- Read SIMs power register (MSB)
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-- i2c_data_to_master <= reg_sim_pwr(15 downto 8);
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-- i2c_slv_state <= wait_while_sent;
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when x"0A" => -- Read SIMs detect register (LSB)
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i2c_data_to_master <= reg_sim_det(7 downto 0);
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i2c_slv_state <= wait_while_sent;
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-- when x"0B" => -- Read SIMs detect register (MSB)
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-- i2c_data_to_master <= reg_sim_det(15 downto 8);
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-- i2c_slv_state <= wait_while_sent;
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when x"0C" => -- Read SIMs power register (LSB)
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i2c_data_to_master <= reg_sim_pwr(7 downto 0);
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i2c_slv_state <= wait_while_sent;
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-- when x"0D" => -- Read SIMs power register (MSB)
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-- i2c_data_to_master <= reg_sim_pwr(15 downto 8);
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-- i2c_slv_state <= wait_while_sent;
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-- when x"1A" => -- Read M1 SIM select register
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-- i2c_data_to_master <= "000000" & reg_sim_sel(0);
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-- i2c_slv_state <= wait_while_sent;
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-- when x"1B" => -- Read M2 SIM select register
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-- i2c_data_to_master <= "000000" & reg_sim_sel(1);
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-- i2c_slv_state <= wait_while_sent;
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-- when x"1C" => -- Read M3 SIM select register
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-- i2c_data_to_master <= "000000" & reg_sim_sel(2);
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-- i2c_slv_state <= wait_while_sent;
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-- when x"1D" => -- Read M4 SIM select register
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-- i2c_data_to_master <= "000000" & reg_sim_sel(3);
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-- i2c_slv_state <= wait_while_sent;
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when x"20" => -- Read SIM1 modem register
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i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(0),4));
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i2c_slv_state <= wait_while_sent;
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when x"21" => -- Read SIM2 modem register
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i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(1),4));
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i2c_slv_state <= wait_while_sent;
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when x"22" => -- Read SIM3 modem register
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i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(2),4));
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i2c_slv_state <= wait_while_sent;
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when x"23" => -- Read SIM4 modem register
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i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(3),4));
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i2c_slv_state <= wait_while_sent;
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when x"24" => -- Read SIM5 modem register
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i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(4),4));
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i2c_slv_state <= wait_while_sent;
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when x"25" => -- Read SIM6 modem register
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i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(5),4));
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i2c_slv_state <= wait_while_sent;
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when x"26" => -- Read SIM7 modem register
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i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(6),4));
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i2c_slv_state <= wait_while_sent;
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when x"27" => -- Read SIM8 modem register
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i2c_data_to_master <= "0000" & std_logic_vector(to_unsigned(reg_sim_modemnum(7),4));
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i2c_slv_state <= wait_while_sent;
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-- when x"8C" => -- Write SIMs power register (LSB)
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-- i2c_slv_state <= receive_byte;
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-- when x"8D" => -- Write SIMs power register (MSB)
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-- i2c_slv_state <= receive_byte;
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when x"8C" => -- Write SIMs power register (LSB)
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i2c_slv_state <= receive_byte;
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-- when x"8D" => -- Write SIMs power register (MSB)
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-- i2c_slv_state <= receive_byte;
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-- when x"9A" => -- Write M1 select register
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-- i2c_slv_state <= receive_byte;
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-- when x"9B" => -- Write M2 select register
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-- i2c_slv_state <= receive_byte;
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-- when x"9C" => -- Write M3 select register
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-- i2c_slv_state <= receive_byte;
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-- when x"9D" => -- Write M4 select register
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-- i2c_slv_state <= receive_byte;
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when x"A0" => -- Write SIM1 modem register
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i2c_slv_state <= receive_byte;
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when x"A1" => -- Write SIM2 modem register
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i2c_slv_state <= receive_byte;
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when x"A2" => -- Write SIM3 modem register
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i2c_slv_state <= receive_byte;
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when x"A3" => -- Write SIM4 modem register
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i2c_slv_state <= receive_byte;
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when x"A4" => -- Write SIM5 modem register
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i2c_slv_state <= receive_byte;
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when x"A5" => -- Write SIM6 modem register
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i2c_slv_state <= receive_byte;
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when x"A6" => -- Write SIM7 modem register
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i2c_slv_state <= receive_byte;
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when x"A7" => -- Write SIM8 modem register
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i2c_slv_state <= receive_byte;
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-- when others =>
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-- i2c_slv_state <= ready;
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-- end case;
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-- end if;
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when others =>
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i2c_slv_state <= ready;
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end case;
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end if;
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-- when receive_byte =>
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-- if (i2c_data_valid = '1') then
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-- case s_reg_to_write is
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-- when x"8C" => -- Write SIMs power register (LSB)
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-- reg_sim_pwr(7 downto 0) <= i2c_data_from_master(7 downto 0);
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-- when x"8D" => -- Write SIMs power register (MSB)
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-- reg_sim_pwr(15 downto 8) <= i2c_data_from_master(7 downto 0);
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when receive_byte =>
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if (i2c_data_valid = '1') then
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case s_reg_to_write is
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when x"8C" => -- Write SIMs power register (LSB)
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reg_sim_pwr(7 downto 0) <= i2c_data_from_master(7 downto 0);
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-- when x"8D" => -- Write SIMs power register (MSB)
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-- reg_sim_pwr(15 downto 8) <= i2c_data_from_master(7 downto 0);
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-- when x"9A" => -- Write M1 select register
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-- reg_sim_sel(0) <= i2c_data_from_master(1 downto 0);
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-- when x"9B" => -- Write M2 select register
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-- reg_sim_sel(1) <= i2c_data_from_master(1 downto 0);
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-- when x"9C" => -- Write M3 select register
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-- reg_sim_sel(2) <= i2c_data_from_master(1 downto 0);
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-- when x"9D" => -- Write M4 select register
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-- reg_sim_sel(3) <= i2c_data_from_master(1 downto 0);
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-- when others =>
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-- null;
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-- end case;
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-- i2c_slv_state <= ready;
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-- else
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-- -- Wait timer to prevent freeze in waiting state
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-- if (wait_cnt > I2C_MAX_WAIT) then
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-- i2c_slv_state <= ready;
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-- else
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-- wait_cnt := wait_cnt + 1;
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-- end if;
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-- end if;
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when x"A0" => -- Write SIM1 modem register
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reg_sim_modemnum(0) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
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when x"A1" => -- Write SIM2 modem register
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reg_sim_modemnum(1) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
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when x"A2" => -- Write SIM3 modem register
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reg_sim_modemnum(2) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
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when x"A3" => -- Write SIM4 modem register
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reg_sim_modemnum(3) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
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when x"A4" => -- Write SIM1 modem register
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reg_sim_modemnum(4) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
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when x"A5" => -- Write SIM2 modem register
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reg_sim_modemnum(5) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
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when x"A6" => -- Write SIM3 modem register
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reg_sim_modemnum(6) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
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when x"A7" => -- Write SIM4 modem register
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reg_sim_modemnum(7) <= to_integer(unsigned(i2c_data_from_master(3 downto 0)));
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-- when wait_while_sent =>
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-- if (i2c_read_req = '1') then
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-- i2c_slv_state <= ready;
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-- else
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-- -- Wait timer to prevent freeze in waiting state
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-- if (wait_cnt > I2C_MAX_WAIT) then
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-- i2c_slv_state <= ready;
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-- else
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-- wait_cnt := wait_cnt + 1;
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-- end if;
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-- end if;
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when others =>
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null;
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end case;
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i2c_slv_state <= ready;
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else
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-- Wait timer to prevent freeze in waiting state
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if (wait_cnt > I2C_MAX_WAIT) then
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i2c_slv_state <= ready;
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else
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wait_cnt := wait_cnt + 1;
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end if;
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end if;
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-- when others =>
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-- i2c_slv_state <= ready;
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when wait_while_sent =>
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if (i2c_read_req = '1') then
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i2c_slv_state <= ready;
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else
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-- Wait timer to prevent freeze in waiting state
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if (wait_cnt > I2C_MAX_WAIT) then
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i2c_slv_state <= ready;
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else
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wait_cnt := wait_cnt + 1;
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end if;
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end if;
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||||
-- end case;
|
||||
-- end if;
|
||||
-- end process i2c_slv_process;
|
||||
when others =>
|
||||
i2c_slv_state <= ready;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process i2c_slv_process;
|
||||
|
||||
-------------------------------
|
||||
--- SIM card emulation test ---
|
||||
|
|
@ -577,7 +611,7 @@ begin
|
|||
else 'Z';
|
||||
|
||||
-- Route one-way signals from mod to SIM
|
||||
sim_pwron_o <= (others => '1');--mod_pwron_i;
|
||||
sim_pwron_o <= reg_sim_pwr(7 downto 0);--(others => '1');--mod_pwron_i;
|
||||
--mod_detect_o(3 downto 0) <= sim_detect_i(3 downto 0); --!! Switching
|
||||
|
||||
-- Bidir sinals routing
|
||||
|
|
|
|||
Loading…
Reference in New Issue