Mostly tested on MBSr2, SIMs not tested, not working: PSE I2C
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matt
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@ -113,6 +113,10 @@ architecture rtl of sim_switcher_top is
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constant SB_CONF_UPDATE_INTERVAL : natural := 25_000_000; -- 25_000_000 = 1sec
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constant DEBOUNCING_WAIT_CYCLES : natural := 3; -- Number of debouncing wait cycles
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constant REPI2C_DEBOUNCING_WAIT_CYCLES : natural := 3; -- Number of debouncing wait cycles
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constant EXPIO_DEBOUNCING_WAIT_CYCLES : natural := 25; -- Number of debouncing wait cycles
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constant I2C_CLK : natural := 400_000; -- speed the i2c bus (scl) will run at in Hz
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constant I2C_MAX_WAIT : natural := 2_500_000; -- 25_000_000 = 1sec
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@ -241,36 +245,189 @@ begin
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fan_o <= reg_fan_ctl;
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-- PSE init
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pse_rst <= reg_pse_ctl(0);
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pse_vpwr_enn <= reg_pse_ctl(1);
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reg_pse_status <= pse_intn&pse_vpwr_pg;
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pse_rst <= reg_pse_ctl(0);
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pse_vpwr_enn <= reg_pse_ctl(1);
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reg_pse_status(1) <= not pse_intn;
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reg_pse_status(0) <= pse_vpwr_pg;
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-- Connect PSE I2C bus to main I2C bus
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pse_scl_rptr: odio_repeater
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generic map (
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WAIT_CYCLES => DEBOUNCING_WAIT_CYCLES
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)
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port map (
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clk => clk25_i,
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rstn => s_rstn_i,
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signal_n1 => i2c_scl_io,
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signal_n2 => pse_i2c_scl_io
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);
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-- inst_i2c_master: i2c_master
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-- generic map (
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-- input_clk => SYSFREQ,
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-- bus_clk => I2C_CLK
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-- )
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-- port map (
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-- clk => clk25_i,
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-- reset_n => s_rstn_i,
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-- ena => s_i2c_txn_start,
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-- addr => x"20",
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-- rw => s_i2c_rw_flag,
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-- data_wr => s_i2c_data_wr,
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-- busy => s_i2c_busy_flag,
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-- data_rd => s_i2c_data_rd,
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-- ack_error => open,
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-- sda => pse_i2c_sda_io,
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-- scl => pse_i2c_scl_io,
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-- scl_invert => '0'
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-- );
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pse_sda_rptr: odio_repeater
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generic map (
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WAIT_CYCLES => DEBOUNCING_WAIT_CYCLES
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)
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port map (
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clk => clk25_i,
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rstn => s_rstn_i,
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signal_n1 => i2c_sda_io,
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signal_n2 => pse_i2c_sda_io
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);
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-- -- PSE I2C interaction process
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-- pse_i2c_proc: process (clk_i, rstn_i)
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-- variable data_wr_cnt : natural := 0;
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-- variable data_rd_cnt : natural := 0;
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-- begin
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-- if (rstn_i = '0') then
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-- i2c_state <= ready;
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-- i2c_core_busy <= '0';
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-- i2c_busy_prev <= (others => '0');
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-- i2c_ram_we <= (others => '0');
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-- i2c_wr_done <= '0';
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-- elsif (rising_edge(clk_i)) then
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-- case i2c_state is
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-- when ready =>
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-- if (i2c_core_start = '1') then
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-- i2c_state <= i2c_trn_start;
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-- i2c_core_busy <= '1';
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-- data_wr_cnt := 0;
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-- data_rd_cnt := 0;
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-- spi_ram_raddr <= data_wr_cnt; -- Request data from RAM
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-- i2c_busy_prev <= (i2c_busy_prev'range => '0');
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-- end if;
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-- when i2c_trn_start =>
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-- i2c_txn_start_o <= reg_i2c_mask; -- Initiate the transaction
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-- i2c_slv_addr_o <= (others => reg_i2c_addr); -- Set the address of the slave
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-- i2c_rw_flag_o <= (others => '0'); -- First byte is always write
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-- i2c_data_wr_o <= (others => spi_ram_data_o); -- Data to be written
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-- i2c_state <= i2c_trn_main;
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-- when i2c_trn_main =>
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-- i2c_data_wr_o <= (others => spi_ram_data_o); -- Data to be written to the I2C buses
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-- i2c_busy_prev <= i2c_busy_flag_i; -- Capture the value of the previous i2c busy signal
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-- if (i2c_busy_prev = (i2c_busy_prev'range => '0') and i2c_busy_flag_i = reg_i2c_mask) then -- I2C busy just went high
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-- case reg_i2c_trn_dir is -- Switches to the needed transaction direction
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-- when '0' => -- When write - continue to write
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-- data_wr_cnt := data_wr_cnt + 1;
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-- if (data_wr_cnt > 0 and data_wr_cnt < spi_command_len) then -- Keep writing if there's still data in the RAM
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-- spi_ram_raddr <= data_wr_cnt;
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-- i2c_state <= wait_ram;
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-- else -- Else - finish the transaction
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-- i2c_state <= i2c_trn_final_word_wait;
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-- i2c_txn_start_o <= (others => '0');
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-- end if;
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-- when '1' => -- When read
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-- if (data_rd_cnt = 0 and i2c_wr_done = '0') then -- Change the transaction from Write to Read after writing the first byte
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-- i2c_rw_flag_o <= (others => '1');
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-- i2c_state <= i2c_wr_wait; -- Switch to read
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-- else
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-- i2c_state <= i2c_rd_wait;
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-- i2c_wr_done <= '0';
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-- end if;
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-- i2c_ram_we <= (others => '0');
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-- when others =>
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-- i2c_state <= ready;
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-- end case;
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-- end if;
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-- when wait_ram =>
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-- i2c_state <= i2c_trn_main;
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-- when i2c_trn_final_word_wait =>
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-- if (i2c_busy_prev = reg_i2c_mask and i2c_busy_flag_i = (i2c_busy_prev'range => '0')) then -- I2C became free
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-- i2c_state <= wait_ack;
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-- end if;
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-- when i2c_wr_wait =>
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-- if (i2c_busy_flag_i = (i2c_busy_flag_i'range => '0')) then -- Indicates data read in last command is ready
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-- i2c_state <= i2c_trn_main; -- Transaction complete, go to next state in design
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-- i2c_wr_done <= '1';
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-- end if;
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-- when i2c_rd_wait =>
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-- if (i2c_busy_flag_i = (i2c_busy_flag_i'range => '0')) then -- Indicates data read in last command is ready
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-- data_rd_cnt := data_rd_cnt + 1;
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-- i2c_ram_waddr <= (others => data_rd_cnt-1);
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-- i2c_ram_we <= reg_i2c_mask;
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-- for i in 0 to I2C_NUM-1 loop
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-- if (reg_i2c_mask(i) = '1') then
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-- i2c_ram_data_i(i) <= i2c_data_rd_i(i); -- Store received byte
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-- end if;
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-- end loop;
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-- if (data_rd_cnt = reg_i2c_read_len) then
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-- i2c_state <= wait_ack; -- Transaction complete, go to next state in design
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-- else
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-- i2c_state <= i2c_trn_main; -- Transaction complete, go to next state in design
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-- end if;
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-- end if;
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-- if (data_rd_cnt+1 = reg_i2c_read_len) then
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-- i2c_txn_start_o <= (others => '0');
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-- end if;
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-- when wait_ack =>
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-- i2c_core_busy <= '0';
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-- i2c_ram_we <= (others => '0');
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-- i2c_busy_prev <= (others => '0');
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-- if (i2c_core_start = '0') then
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-- i2c_state <= ready;
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-- end if;
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-- when others =>
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-- i2c_state <= ready;
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-- end case;
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-- end if;
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-- end process pse_i2c_proc;
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-- s_i2c_txn_start
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-- s_i2c_rw_flag
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-- s_i2c_data_wr
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-- s_i2c_busy_flag
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-- s_i2c_data_rd
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-- pse_scl_rptr: odio_repeater
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-- generic map (
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-- WAIT_CYCLES => REPI2C_DEBOUNCING_WAIT_CYCLES
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-- )
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-- port map (
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-- clk => clk25_i,
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-- rstn => s_rstn_i,
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-- signal_n1 => i2c_scl_io,
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-- signal_n2 => pse_i2c_scl_io
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-- );
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-- pse_sda_rptr: odio_repeater
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-- generic map (
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-- WAIT_CYCLES => REPI2C_DEBOUNCING_WAIT_CYCLES
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-- )
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-- port map (
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-- clk => clk25_i,
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-- rstn => s_rstn_i,
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-- signal_n1 => i2c_sda_io,
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-- signal_n2 => pse_i2c_sda_io
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-- );
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-- pse_i2c_rptr: i2c_repeater
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-- generic map (
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-- WAIT_CYCLES => REPI2C_DEBOUNCING_WAIT_CYCLES
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-- )
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-- port map (
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-- clk => clk25_i,
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-- rstn => s_rstn_i,
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-- pr_scl => i2c_scl_io,
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-- pr_sda => i2c_sda_io,
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-- sec_scl => pse_i2c_scl_io,
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-- sec_sda => pse_i2c_sda_io
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-- );
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-- POE PD init
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reg_poepd_status <= poe_in_vpres&poe_in_t2p;
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poe_in_enn <= reg_poepd_ctl;
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reg_poepd_status(2) <= poe_in_vpres;
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reg_poepd_status(1 downto 0) <= poe_in_t2p(1 downto 0);
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poe_in_enn <= reg_poepd_ctl;
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-- Expansion card IO control
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gen_expio_dbnc: for i in 0 to 5 generate
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@ -283,7 +440,7 @@ begin
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expio_debounce : debounce
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generic map (
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WAIT_CYCLES => DEBOUNCING_WAIT_CYCLES
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WAIT_CYCLES => EXPIO_DEBOUNCING_WAIT_CYCLES
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)
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port map (
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clk => clk25_i,
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