63 lines
2.7 KiB
VHDL
63 lines
2.7 KiB
VHDL
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
|
|
package sim_switcher_pkg is
|
|
|
|
type arr_modnum_t is array (natural range <>) of natural range 0 to 15;
|
|
|
|
component sim_mux is
|
|
port (
|
|
reg_sim_modemnum : arr_modnum_t(0 to 7);
|
|
sim_rst_o : out std_logic_vector(7 downto 0);
|
|
mod_simrst_i : in std_logic_vector(7 downto 0);
|
|
sim_clk_o : out std_logic_vector(7 downto 0);
|
|
mod_clk_i : in std_logic_vector(7 downto 0);
|
|
mod_detect_o : out std_logic_vector(3 downto 0);
|
|
sim_detect_i : in std_logic_vector(7 downto 0);
|
|
sw_mod_data_i : out std_logic_vector(7 downto 0); -- For switched tri-state buffer there are input and output part of
|
|
mod_data_i : in std_logic_vector(7 downto 0); -- the lines which are switched transparently, thus ports
|
|
mod_data_o : out std_logic_vector(7 downto 0); -- sw_mod_data_i is actual output and sw_mod_data_o is
|
|
sw_mod_data_o : in std_logic_vector(7 downto 0) -- actual input. Please, don't be confused.
|
|
);
|
|
end component sim_mux;
|
|
|
|
component i2c_master IS
|
|
generic (
|
|
input_clk : integer := 50_000_000; --input clock speed from user logic in Hz
|
|
bus_clk : integer := 400_000 --speed the i2c bus (scl) will run at in Hz
|
|
);
|
|
port (
|
|
clk : in std_logic; --system clock
|
|
reset_n : in std_logic; --active low reset
|
|
ena : in std_logic; --latch in command
|
|
addr : in std_logic_vector(6 downto 0); --address of target slave
|
|
rw : in std_logic; --'0' is write, '1' is read
|
|
data_wr : in std_logic_vector(7 downto 0); --data to write to slave
|
|
busy : out std_logic; --indicates transaction in progress
|
|
data_rd : out std_logic_vector(7 downto 0); --data read from slave
|
|
ack_error : buffer std_logic; --flag if improper acknowledge from slave
|
|
sda : inout std_logic; --serial data output of i2c bus
|
|
scl : inout std_logic; --serial clock output of i2c bus
|
|
scl_invert: in std_logic --true if need to invert output SCL signal
|
|
);
|
|
end component i2c_master;
|
|
|
|
component i2c_slave is
|
|
generic (
|
|
SLAVE_ADDR : std_logic_vector(6 downto 0)
|
|
);
|
|
port (
|
|
scl : inout std_logic;
|
|
sda : inout std_logic;
|
|
clk : in std_logic;
|
|
rst : in std_logic;
|
|
-- User interface
|
|
read_req : out std_logic;
|
|
data_to_master : in std_logic_vector(7 downto 0);
|
|
data_valid : out std_logic;
|
|
data_from_master : out std_logic_vector(7 downto 0)
|
|
);
|
|
end component i2c_slave;
|
|
|
|
end package sim_switcher_pkg; |