Working muxing with stationary MUX register
This commit is contained in:
matt
parent
0ccef67d9a
commit
86c7da5075
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@ -0,0 +1,301 @@
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------------------------------------------------------------
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-- File : I2C_slave.vhd
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------------------------------------------------------------
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-- Author : Peter Samarin <peter.samarin@gmail.com>
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------------------------------------------------------------
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-- Copyright (c) 2016 Peter Samarin
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------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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------------------------------------------------------------
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entity i2c_slave is
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generic (
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SLAVE_ADDR : std_logic_vector(6 downto 0));
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port (
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scl : inout std_logic;
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sda : inout std_logic;
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clk : in std_logic;
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rst : in std_logic;
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-- User interface
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read_req : out std_logic;
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data_to_master : in std_logic_vector(7 downto 0);
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data_valid : out std_logic;
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data_from_master : out std_logic_vector(7 downto 0));
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end entity i2c_slave;
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------------------------------------------------------------
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architecture arch of i2c_slave is
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-- this assumes that system's clock is much faster than SCL
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constant DEBOUNCING_WAIT_CYCLES : integer := 4;
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type state_t is (idle, get_address_and_cmd,
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answer_ack_start, write,
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read, read_ack_start,
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read_ack_got_rising, read_stop);
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-- I2C state management
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signal state_reg : state_t := idle;
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signal cmd_reg : std_logic := '0';
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signal bits_processed_reg : integer range 0 to 8 := 0;
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signal continue_reg : std_logic := '0';
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signal scl_reg : std_logic := '1';
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signal sda_reg : std_logic := '1';
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signal scl_debounced : std_logic := '1';
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signal sda_debounced : std_logic := '1';
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-- Helpers to figure out next state
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signal start_reg : std_logic := '0';
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signal stop_reg : std_logic := '0';
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signal scl_rising_reg : std_logic := '0';
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signal scl_falling_reg : std_logic := '0';
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-- Address and data received from master
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signal addr_reg : std_logic_vector(6 downto 0) := (others => '0');
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signal data_reg : std_logic_vector(6 downto 0) := (others => '0');
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signal data_from_master_reg : std_logic_vector(7 downto 0) := (others => '0');
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signal scl_prev_reg : std_logic := '1';
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-- Slave writes on scl
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signal scl_wen_reg : std_logic := '0';
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signal scl_o_reg : std_logic := '0';
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signal sda_prev_reg : std_logic := '1';
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-- Slave writes on sda
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signal sda_wen_reg : std_logic := '0';
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signal sda_o_reg : std_logic := '0';
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-- User interface
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signal data_valid_reg : std_logic := '0';
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signal read_req_reg : std_logic := '0';
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signal data_to_master_reg : std_logic_vector(7 downto 0) := (others => '0');
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begin
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-- debounce SCL and SDA
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SCL_debounce : entity work.debounce
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generic map (
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WAIT_CYCLES => DEBOUNCING_WAIT_CYCLES)
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port map (
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clk => clk,
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signal_in => scl_reg,
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signal_out => scl_debounced);
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-- it might not make sense to debounce SDA, since master
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-- and slave can both write to it...
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SDA_debounce : entity work.debounce
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generic map (
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WAIT_CYCLES => DEBOUNCING_WAIT_CYCLES)
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port map (
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clk => clk,
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signal_in => sda_reg,
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signal_out => sda_debounced);
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process (clk) is
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begin
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if rising_edge(clk) then
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-- save SCL in registers that are used for debouncing
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scl_reg <= scl;
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sda_reg <= sda;
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-- Delay debounced SCL and SDA by 1 clock cycle
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scl_prev_reg <= scl_debounced;
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sda_prev_reg <= sda_debounced;
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-- Detect rising and falling SCL
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scl_rising_reg <= '0';
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if scl_prev_reg = '0' and scl_debounced = '1' then
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scl_rising_reg <= '1';
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end if;
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scl_falling_reg <= '0';
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if scl_prev_reg = '1' and scl_debounced = '0' then
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scl_falling_reg <= '1';
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end if;
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-- Detect I2C START condition
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start_reg <= '0';
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stop_reg <= '0';
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if scl_debounced = '1' and scl_prev_reg = '1' and
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sda_prev_reg = '1' and sda_debounced = '0' then
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start_reg <= '1';
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stop_reg <= '0';
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end if;
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-- Detect I2C STOP condition
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if scl_prev_reg = '1' and scl_debounced = '1' and
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sda_prev_reg = '0' and sda_debounced = '1' then
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start_reg <= '0';
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stop_reg <= '1';
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end if;
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end if;
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end process;
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----------------------------------------------------------
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-- I2C state machine
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----------------------------------------------------------
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process (clk) is
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begin
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if rising_edge(clk) then
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-- Default assignments
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sda_o_reg <= '0';
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sda_wen_reg <= '0';
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-- User interface
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data_valid_reg <= '0';
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read_req_reg <= '0';
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case state_reg is
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when idle =>
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if start_reg = '1' then
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state_reg <= get_address_and_cmd;
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bits_processed_reg <= 0;
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end if;
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when get_address_and_cmd =>
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if scl_rising_reg = '1' then
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if bits_processed_reg < 7 then
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bits_processed_reg <= bits_processed_reg + 1;
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addr_reg(6-bits_processed_reg) <= sda_debounced;
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elsif bits_processed_reg = 7 then
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bits_processed_reg <= bits_processed_reg + 1;
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cmd_reg <= sda_debounced;
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end if;
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end if;
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if bits_processed_reg = 8 and scl_falling_reg = '1' then
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bits_processed_reg <= 0;
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if addr_reg = SLAVE_ADDR then -- check req address
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state_reg <= answer_ack_start;
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if cmd_reg = '1' then -- issue read request
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read_req_reg <= '1';
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data_to_master_reg <= data_to_master;
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end if;
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else
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assert false
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report ("I2C: target/slave address mismatch (data is being sent to another slave).")
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severity note;
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state_reg <= idle;
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end if;
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end if;
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----------------------------------------------------
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-- I2C acknowledge to master
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----------------------------------------------------
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when answer_ack_start =>
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sda_wen_reg <= '1';
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sda_o_reg <= '0';
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if scl_falling_reg = '1' then
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if cmd_reg = '0' then
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state_reg <= write;
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else
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state_reg <= read;
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end if;
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end if;
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----------------------------------------------------
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-- WRITE
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----------------------------------------------------
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when write =>
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if scl_rising_reg = '1' then
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bits_processed_reg <= bits_processed_reg + 1;
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if bits_processed_reg < 7 then
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data_reg(6-bits_processed_reg) <= sda_debounced;
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else
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data_from_master_reg <= data_reg & sda_debounced;
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data_valid_reg <= '1';
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end if;
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end if;
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if scl_falling_reg = '1' and bits_processed_reg = 8 then
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state_reg <= answer_ack_start;
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bits_processed_reg <= 0;
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end if;
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----------------------------------------------------
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-- READ: send data to master
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----------------------------------------------------
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when read =>
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sda_wen_reg <= '1';
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sda_o_reg <= data_to_master_reg(7-bits_processed_reg);
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if scl_falling_reg = '1' then
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if bits_processed_reg < 7 then
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bits_processed_reg <= bits_processed_reg + 1;
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elsif bits_processed_reg = 7 then
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state_reg <= read_ack_start;
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bits_processed_reg <= 0;
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end if;
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end if;
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----------------------------------------------------
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-- I2C read master acknowledge
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----------------------------------------------------
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when read_ack_start =>
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if scl_rising_reg = '1' then
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state_reg <= read_ack_got_rising;
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if sda_debounced = '1' then -- nack = stop read
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continue_reg <= '0';
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else -- ack = continue read
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continue_reg <= '1';
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read_req_reg <= '1'; -- request reg byte
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data_to_master_reg <= data_to_master;
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end if;
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end if;
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when read_ack_got_rising =>
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if scl_falling_reg = '1' then
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if continue_reg = '1' then
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if cmd_reg = '0' then
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state_reg <= write;
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else
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state_reg <= read;
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end if;
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else
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state_reg <= read_stop;
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end if;
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end if;
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-- Wait for START or STOP to get out of this state
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when read_stop =>
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null;
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-- Wait for START or STOP to get out of this state
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when others =>
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assert false
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report ("I2C: error: ended in an impossible state.")
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severity error;
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state_reg <= idle;
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end case;
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--------------------------------------------------------
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-- Reset counter and state on start/stop
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--------------------------------------------------------
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if start_reg = '1' then
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state_reg <= get_address_and_cmd;
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bits_processed_reg <= 0;
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end if;
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if stop_reg = '1' then
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state_reg <= idle;
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bits_processed_reg <= 0;
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end if;
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if rst = '1' then
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state_reg <= idle;
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end if;
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end if;
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end process;
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----------------------------------------------------------
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-- I2C interface
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----------------------------------------------------------
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sda <= sda_o_reg when sda_wen_reg = '1' else
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'Z';
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scl <= scl_o_reg when scl_wen_reg = '1' else
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'Z';
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----------------------------------------------------------
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-- User interface
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----------------------------------------------------------
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-- Master writes
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data_valid <= data_valid_reg;
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data_from_master <= data_from_master_reg;
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-- Master reads
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read_req <= read_req_reg;
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end architecture arch;
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@ -0,0 +1,24 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package sim_switcher_pkg is
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component i2c_slave is
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generic (
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SLAVE_ADDR : std_logic_vector(6 downto 0)
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);
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port (
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scl : inout std_logic;
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sda : inout std_logic;
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clk : in std_logic;
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rst : in std_logic;
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-- User interface
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read_req : out std_logic;
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data_to_master : in std_logic_vector(7 downto 0);
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data_valid : out std_logic;
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data_from_master : out std_logic_vector(7 downto 0)
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);
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end component i2c_slave;
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end package sim_switcher_pkg;
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@ -1,7 +1,7 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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--use work.sim_switcher_pkg.all;
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use work.sim_switcher_pkg.all;
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entity sim_switcher_top is
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generic (
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@ -63,7 +63,7 @@ architecture rtl of sim_switcher_top is
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);
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end component;
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constant FLASHES : natural := 1; -- Number of LED flashes on boot
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constant FLASHES : natural := 5; -- Number of LED flashes on boot
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constant CPU_RST_DURATION : natural := 100_000_000; -- 25_000_000 = 1sec
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constant PON_RST_DURATION : natural := 10; -- 25_000_000 = 1sec
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constant PON_CPU_DELAY_DURATION : natural := 75_000_000; -- 25_000_000 = 1sec
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@ -85,16 +85,55 @@ architecture rtl of sim_switcher_top is
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signal s_led_o : std_logic := '1';
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-- I2C slave parallel interface
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signal i2c_read_req : std_logic := '0';
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signal i2c_data_to_master : std_logic_vector(7 downto 0) := (others => '0');
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signal i2c_data_valid : std_logic := '0';
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signal i2c_data_from_master : std_logic_vector(7 downto 0) := (others => '0');
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-- I2C slave state machine
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type i2c_fsm_t is (ready, receive_byte, wait_while_sent);
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signal i2c_slv_state : i2c_fsm_t := ready;
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-- signal reg_sim_sel : sim_mux_addr_t(3 downto 0);
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-- signal reg_sim_pwr : std_logic_vector(15 downto 0);
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-- signal reg_sim_det : std_logic_vector(15 downto 0);
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-- signal s_reg_to_write : std_logic_vector(7 downto 0);
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-- SIM data signals
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signal s_sim_data_i, sdb_sim_data_i, sdb_sim_data_prev, s_sim_data_o: std_logic_vector(7 downto 0);
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signal s_sim_data_i, sdb_sim_data_i, sdb_sim_data_prev, s_sim_data_o: std_logic_vector(15 downto 0);
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-- Modem data signals
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signal s_mod_data_i, sdb_mod_data_i, sdb_mod_data_prev, s_mod_data_o: std_logic_vector(7 downto 0);
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signal s_mod_data_i, sdb_mod_data_i, sw_mod_data_i, sw_mod_data_prev, s_mod_data_o, sw_mod_data_o: std_logic_vector(7 downto 0);
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-- SIM switch IRQs for repeater state machine reset upon SIM change
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signal reg_sim_change_irq: std_logic_vector(15 downto 0) := (others => '0');
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-- State machine signals and types
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type state_t is (idle, mod_to_sim, sim_to_mod);
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type arr_state_t is array (integer range <>) of state_t;
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type arr_state_t is array (natural range <>) of state_t;
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signal state: arr_state_t(0 to 7);
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-- SIM-MODEM switching register
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type arr_modnum_t is array (natural range <>) of natural range 0 to 15;
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signal reg_sim_modemnum: arr_modnum_t(0 to 7);
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begin
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s_sim_data_i(15 downto 8) <= (others => '1');
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sdb_sim_data_i(15 downto 8) <= (others => '1');
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reg_sim_modemnum <= (
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0 => 7,
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1 => 6,
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2 => 5,
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3 => 4,
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4 => 3,
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5 => 2,
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6 => 1,
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7 => 0
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);
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reg_sim_change_irq <= (others => '0');
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----------------------------------
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-- Power-On FPGA IP-cores reset --
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@ -191,10 +230,355 @@ begin
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end if;
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end process;
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--------------------------------
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-- I2C slave interface to CPU --
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--------------------------------
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-- inst_i2c_slave: i2c_slave
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-- generic map (
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-- SLAVE_ADDR => I2C_SLAVE_ADDR
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-- )
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-- port map(
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-- scl => i2c_scl_io,
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-- sda => i2c_sda_io,
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-- clk => clk25_i,
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-- rst => s_rst_i,
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-- read_req => i2c_read_req,
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-- data_to_master => i2c_data_to_master,
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-- data_valid => i2c_data_valid,
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-- data_from_master => i2c_data_from_master
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-- );
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-- i2c_slv_process : process (clk25_i, s_rstn_i)
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-- variable wait_cnt : natural := 0;
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-- begin
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-- if (s_rstn_i = '0') then
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-- i2c_data_to_master <= (others => '0');
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-- wait_cnt := 0;
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-- -- SIM select reset: default is SIM#1
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-- reg_sim_sel <= (others => (others => '0'));
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-- -- Turn on all SIM cards
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-- reg_sim_pwr <= (others => '1');
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-- -- Only first SIMs are powered on upon reset
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-- -- reg_sim_pwr(0) <= '1';
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-- -- reg_sim_pwr(3 downto 1) <= (others => '0');
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-- --
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-- -- reg_sim_pwr(4) <= '1';
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-- -- reg_sim_pwr(7 downto 5) <= (others => '0');
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-- --
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-- -- reg_sim_pwr(8) <= '1';
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-- -- reg_sim_pwr(11 downto 9) <= (others => '0');
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-- --
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-- -- reg_sim_pwr(12) <= '1';
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-- -- reg_sim_pwr(15 downto 13) <= (others => '0');
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--
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-- reg_sim_change_irq <= (others => '0');
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--
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-- elsif (rising_edge(clk25_i)) then
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-- case i2c_slv_state is
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-- when ready =>
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-- wait_cnt := 0;
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-- i2c_data_to_master <= (others => '0');
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-- if (i2c_data_valid = '1') then -- master sent a register addr byte
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-- -- Save register address for later use in write procedure
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-- s_reg_to_write <= i2c_data_from_master;
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|
||||
-- case i2c_data_from_master is
|
||||
-- when x"10" => -- Read ID byte
|
||||
-- i2c_data_to_master <= x"18";
|
||||
-- i2c_slv_state <= wait_while_sent;
|
||||
|
||||
-- when x"11" => -- Read SW Version byte (v1.0=0x18, v1.1=0x19)
|
||||
-- i2c_data_to_master <= x"19";
|
||||
-- i2c_slv_state <= wait_while_sent;
|
||||
|
||||
-- when x"0A" => -- Read SIMs detect register (LSB)
|
||||
-- i2c_data_to_master <= reg_sim_det(7 downto 0);
|
||||
-- i2c_slv_state <= wait_while_sent;
|
||||
-- when x"0B" => -- Read SIMs detect register (MSB)
|
||||
-- i2c_data_to_master <= reg_sim_det(15 downto 8);
|
||||
-- i2c_slv_state <= wait_while_sent;
|
||||
-- when x"0C" => -- Read SIMs power register (LSB)
|
||||
-- i2c_data_to_master <= reg_sim_pwr(7 downto 0);
|
||||
-- i2c_slv_state <= wait_while_sent;
|
||||
-- when x"0D" => -- Read SIMs power register (MSB)
|
||||
-- i2c_data_to_master <= reg_sim_pwr(15 downto 8);
|
||||
-- i2c_slv_state <= wait_while_sent;
|
||||
|
||||
-- when x"1A" => -- Read M1 SIM select register
|
||||
-- i2c_data_to_master <= "000000" & reg_sim_sel(0);
|
||||
-- i2c_slv_state <= wait_while_sent;
|
||||
-- when x"1B" => -- Read M2 SIM select register
|
||||
-- i2c_data_to_master <= "000000" & reg_sim_sel(1);
|
||||
-- i2c_slv_state <= wait_while_sent;
|
||||
-- when x"1C" => -- Read M3 SIM select register
|
||||
-- i2c_data_to_master <= "000000" & reg_sim_sel(2);
|
||||
-- i2c_slv_state <= wait_while_sent;
|
||||
-- when x"1D" => -- Read M4 SIM select register
|
||||
-- i2c_data_to_master <= "000000" & reg_sim_sel(3);
|
||||
-- i2c_slv_state <= wait_while_sent;
|
||||
|
||||
-- when x"8C" => -- Write SIMs power register (LSB)
|
||||
-- i2c_slv_state <= receive_byte;
|
||||
-- when x"8D" => -- Write SIMs power register (MSB)
|
||||
-- i2c_slv_state <= receive_byte;
|
||||
|
||||
-- when x"9A" => -- Write M1 select register
|
||||
-- i2c_slv_state <= receive_byte;
|
||||
-- when x"9B" => -- Write M2 select register
|
||||
-- i2c_slv_state <= receive_byte;
|
||||
-- when x"9C" => -- Write M3 select register
|
||||
-- i2c_slv_state <= receive_byte;
|
||||
-- when x"9D" => -- Write M4 select register
|
||||
-- i2c_slv_state <= receive_byte;
|
||||
|
||||
-- when others =>
|
||||
-- i2c_slv_state <= ready;
|
||||
-- end case;
|
||||
-- end if;
|
||||
|
||||
-- when receive_byte =>
|
||||
-- if (i2c_data_valid = '1') then
|
||||
-- case s_reg_to_write is
|
||||
-- when x"8C" => -- Write SIMs power register (LSB)
|
||||
-- reg_sim_pwr(7 downto 0) <= i2c_data_from_master(7 downto 0);
|
||||
-- when x"8D" => -- Write SIMs power register (MSB)
|
||||
-- reg_sim_pwr(15 downto 8) <= i2c_data_from_master(7 downto 0);
|
||||
|
||||
-- when x"9A" => -- Write M1 select register
|
||||
-- reg_sim_sel(0) <= i2c_data_from_master(1 downto 0);
|
||||
-- when x"9B" => -- Write M2 select register
|
||||
-- reg_sim_sel(1) <= i2c_data_from_master(1 downto 0);
|
||||
-- when x"9C" => -- Write M3 select register
|
||||
-- reg_sim_sel(2) <= i2c_data_from_master(1 downto 0);
|
||||
-- when x"9D" => -- Write M4 select register
|
||||
-- reg_sim_sel(3) <= i2c_data_from_master(1 downto 0);
|
||||
-- when others =>
|
||||
-- null;
|
||||
-- end case;
|
||||
-- i2c_slv_state <= ready;
|
||||
-- else
|
||||
-- -- Wait timer to prevent freeze in waiting state
|
||||
-- if (wait_cnt > I2C_MAX_WAIT) then
|
||||
-- i2c_slv_state <= ready;
|
||||
-- else
|
||||
-- wait_cnt := wait_cnt + 1;
|
||||
-- end if;
|
||||
-- end if;
|
||||
|
||||
-- when wait_while_sent =>
|
||||
-- if (i2c_read_req = '1') then
|
||||
-- i2c_slv_state <= ready;
|
||||
-- else
|
||||
-- -- Wait timer to prevent freeze in waiting state
|
||||
-- if (wait_cnt > I2C_MAX_WAIT) then
|
||||
-- i2c_slv_state <= ready;
|
||||
-- else
|
||||
-- wait_cnt := wait_cnt + 1;
|
||||
-- end if;
|
||||
-- end if;
|
||||
|
||||
-- when others =>
|
||||
-- i2c_slv_state <= ready;
|
||||
|
||||
-- end case;
|
||||
-- end if;
|
||||
-- end process i2c_slv_process;
|
||||
|
||||
-------------------------------
|
||||
--- SIM card emulation test ---
|
||||
-------------------------------
|
||||
-- Switch RST line of SIM according to connected MODEM
|
||||
sim_rst_o(0) <= mod_rst_i(0) when reg_sim_modemnum(0) = 0
|
||||
else mod_rst_i(1) when reg_sim_modemnum(0) = 1
|
||||
else mod_rst_i(2) when reg_sim_modemnum(0) = 2
|
||||
else mod_rst_i(3) when reg_sim_modemnum(0) = 3
|
||||
else mod_rst_i(4) when reg_sim_modemnum(0) = 4
|
||||
else mod_rst_i(5) when reg_sim_modemnum(0) = 5
|
||||
else mod_rst_i(6) when reg_sim_modemnum(0) = 6
|
||||
else mod_rst_i(7) when reg_sim_modemnum(0) = 7
|
||||
else 'Z';
|
||||
sim_rst_o(1) <= mod_rst_i(0) when reg_sim_modemnum(1) = 0
|
||||
else mod_rst_i(1) when reg_sim_modemnum(1) = 1
|
||||
else mod_rst_i(2) when reg_sim_modemnum(1) = 2
|
||||
else mod_rst_i(3) when reg_sim_modemnum(1) = 3
|
||||
else mod_rst_i(4) when reg_sim_modemnum(1) = 4
|
||||
else mod_rst_i(5) when reg_sim_modemnum(1) = 5
|
||||
else mod_rst_i(6) when reg_sim_modemnum(1) = 6
|
||||
else mod_rst_i(7) when reg_sim_modemnum(1) = 7
|
||||
else 'Z';
|
||||
sim_rst_o(2) <= mod_rst_i(0) when reg_sim_modemnum(2) = 0
|
||||
else mod_rst_i(1) when reg_sim_modemnum(2) = 1
|
||||
else mod_rst_i(2) when reg_sim_modemnum(2) = 2
|
||||
else mod_rst_i(3) when reg_sim_modemnum(2) = 3
|
||||
else mod_rst_i(4) when reg_sim_modemnum(2) = 4
|
||||
else mod_rst_i(5) when reg_sim_modemnum(2) = 5
|
||||
else mod_rst_i(6) when reg_sim_modemnum(2) = 6
|
||||
else mod_rst_i(7) when reg_sim_modemnum(2) = 7
|
||||
else 'Z';
|
||||
sim_rst_o(3) <= mod_rst_i(0) when reg_sim_modemnum(3) = 0
|
||||
else mod_rst_i(1) when reg_sim_modemnum(3) = 1
|
||||
else mod_rst_i(2) when reg_sim_modemnum(3) = 2
|
||||
else mod_rst_i(3) when reg_sim_modemnum(3) = 3
|
||||
else mod_rst_i(4) when reg_sim_modemnum(3) = 4
|
||||
else mod_rst_i(5) when reg_sim_modemnum(3) = 5
|
||||
else mod_rst_i(6) when reg_sim_modemnum(3) = 6
|
||||
else mod_rst_i(7) when reg_sim_modemnum(3) = 7
|
||||
else 'Z';
|
||||
sim_rst_o(4) <= mod_rst_i(0) when reg_sim_modemnum(4) = 0
|
||||
else mod_rst_i(1) when reg_sim_modemnum(4) = 1
|
||||
else mod_rst_i(2) when reg_sim_modemnum(4) = 2
|
||||
else mod_rst_i(3) when reg_sim_modemnum(4) = 3
|
||||
else mod_rst_i(4) when reg_sim_modemnum(4) = 4
|
||||
else mod_rst_i(5) when reg_sim_modemnum(4) = 5
|
||||
else mod_rst_i(6) when reg_sim_modemnum(4) = 6
|
||||
else mod_rst_i(7) when reg_sim_modemnum(4) = 7
|
||||
else 'Z';
|
||||
sim_rst_o(5) <= mod_rst_i(0) when reg_sim_modemnum(5) = 0
|
||||
else mod_rst_i(1) when reg_sim_modemnum(5) = 1
|
||||
else mod_rst_i(2) when reg_sim_modemnum(5) = 2
|
||||
else mod_rst_i(3) when reg_sim_modemnum(5) = 3
|
||||
else mod_rst_i(4) when reg_sim_modemnum(5) = 4
|
||||
else mod_rst_i(5) when reg_sim_modemnum(5) = 5
|
||||
else mod_rst_i(6) when reg_sim_modemnum(5) = 6
|
||||
else mod_rst_i(7) when reg_sim_modemnum(5) = 7
|
||||
else 'Z';
|
||||
sim_rst_o(6) <= mod_rst_i(0) when reg_sim_modemnum(6) = 0
|
||||
else mod_rst_i(1) when reg_sim_modemnum(6) = 1
|
||||
else mod_rst_i(2) when reg_sim_modemnum(6) = 2
|
||||
else mod_rst_i(3) when reg_sim_modemnum(6) = 3
|
||||
else mod_rst_i(4) when reg_sim_modemnum(6) = 4
|
||||
else mod_rst_i(5) when reg_sim_modemnum(6) = 5
|
||||
else mod_rst_i(6) when reg_sim_modemnum(6) = 6
|
||||
else mod_rst_i(7) when reg_sim_modemnum(6) = 7
|
||||
else 'Z';
|
||||
sim_rst_o(7) <= mod_rst_i(0) when reg_sim_modemnum(7) = 0
|
||||
else mod_rst_i(1) when reg_sim_modemnum(7) = 1
|
||||
else mod_rst_i(2) when reg_sim_modemnum(7) = 2
|
||||
else mod_rst_i(3) when reg_sim_modemnum(7) = 3
|
||||
else mod_rst_i(4) when reg_sim_modemnum(7) = 4
|
||||
else mod_rst_i(5) when reg_sim_modemnum(7) = 5
|
||||
else mod_rst_i(6) when reg_sim_modemnum(7) = 6
|
||||
else mod_rst_i(7) when reg_sim_modemnum(7) = 7
|
||||
else 'Z';
|
||||
|
||||
-- Switch CLK line of SIM according to connected MODEM
|
||||
sim_clk_o(0) <= mod_clk_i(0) when reg_sim_modemnum(0) = 0
|
||||
else mod_clk_i(1) when reg_sim_modemnum(0) = 1
|
||||
else mod_clk_i(2) when reg_sim_modemnum(0) = 2
|
||||
else mod_clk_i(3) when reg_sim_modemnum(0) = 3
|
||||
else mod_clk_i(4) when reg_sim_modemnum(0) = 4
|
||||
else mod_clk_i(5) when reg_sim_modemnum(0) = 5
|
||||
else mod_clk_i(6) when reg_sim_modemnum(0) = 6
|
||||
else mod_clk_i(7) when reg_sim_modemnum(0) = 7
|
||||
else 'Z';
|
||||
sim_clk_o(1) <= mod_clk_i(0) when reg_sim_modemnum(1) = 0
|
||||
else mod_clk_i(1) when reg_sim_modemnum(1) = 1
|
||||
else mod_clk_i(2) when reg_sim_modemnum(1) = 2
|
||||
else mod_clk_i(3) when reg_sim_modemnum(1) = 3
|
||||
else mod_clk_i(4) when reg_sim_modemnum(1) = 4
|
||||
else mod_clk_i(5) when reg_sim_modemnum(1) = 5
|
||||
else mod_clk_i(6) when reg_sim_modemnum(1) = 6
|
||||
else mod_clk_i(7) when reg_sim_modemnum(1) = 7
|
||||
else 'Z';
|
||||
sim_clk_o(2) <= mod_clk_i(0) when reg_sim_modemnum(2) = 0
|
||||
else mod_clk_i(1) when reg_sim_modemnum(2) = 1
|
||||
else mod_clk_i(2) when reg_sim_modemnum(2) = 2
|
||||
else mod_clk_i(3) when reg_sim_modemnum(2) = 3
|
||||
else mod_clk_i(4) when reg_sim_modemnum(2) = 4
|
||||
else mod_clk_i(5) when reg_sim_modemnum(2) = 5
|
||||
else mod_clk_i(6) when reg_sim_modemnum(2) = 6
|
||||
else mod_clk_i(7) when reg_sim_modemnum(2) = 7
|
||||
else 'Z';
|
||||
sim_clk_o(3) <= mod_clk_i(0) when reg_sim_modemnum(3) = 0
|
||||
else mod_clk_i(1) when reg_sim_modemnum(3) = 1
|
||||
else mod_clk_i(2) when reg_sim_modemnum(3) = 2
|
||||
else mod_clk_i(3) when reg_sim_modemnum(3) = 3
|
||||
else mod_clk_i(4) when reg_sim_modemnum(3) = 4
|
||||
else mod_clk_i(5) when reg_sim_modemnum(3) = 5
|
||||
else mod_clk_i(6) when reg_sim_modemnum(3) = 6
|
||||
else mod_clk_i(7) when reg_sim_modemnum(3) = 7
|
||||
else 'Z';
|
||||
sim_clk_o(4) <= mod_clk_i(0) when reg_sim_modemnum(4) = 0
|
||||
else mod_clk_i(1) when reg_sim_modemnum(4) = 1
|
||||
else mod_clk_i(2) when reg_sim_modemnum(4) = 2
|
||||
else mod_clk_i(3) when reg_sim_modemnum(4) = 3
|
||||
else mod_clk_i(4) when reg_sim_modemnum(4) = 4
|
||||
else mod_clk_i(5) when reg_sim_modemnum(4) = 5
|
||||
else mod_clk_i(6) when reg_sim_modemnum(4) = 6
|
||||
else mod_clk_i(7) when reg_sim_modemnum(4) = 7
|
||||
else 'Z';
|
||||
sim_clk_o(5) <= mod_clk_i(0) when reg_sim_modemnum(5) = 0
|
||||
else mod_clk_i(1) when reg_sim_modemnum(5) = 1
|
||||
else mod_clk_i(2) when reg_sim_modemnum(5) = 2
|
||||
else mod_clk_i(3) when reg_sim_modemnum(5) = 3
|
||||
else mod_clk_i(4) when reg_sim_modemnum(5) = 4
|
||||
else mod_clk_i(5) when reg_sim_modemnum(5) = 5
|
||||
else mod_clk_i(6) when reg_sim_modemnum(5) = 6
|
||||
else mod_clk_i(7) when reg_sim_modemnum(5) = 7
|
||||
else 'Z';
|
||||
sim_clk_o(6) <= mod_clk_i(0) when reg_sim_modemnum(6) = 0
|
||||
else mod_clk_i(1) when reg_sim_modemnum(6) = 1
|
||||
else mod_clk_i(2) when reg_sim_modemnum(6) = 2
|
||||
else mod_clk_i(3) when reg_sim_modemnum(6) = 3
|
||||
else mod_clk_i(4) when reg_sim_modemnum(6) = 4
|
||||
else mod_clk_i(5) when reg_sim_modemnum(6) = 5
|
||||
else mod_clk_i(6) when reg_sim_modemnum(6) = 6
|
||||
else mod_clk_i(7) when reg_sim_modemnum(6) = 7
|
||||
else 'Z';
|
||||
sim_clk_o(7) <= mod_clk_i(0) when reg_sim_modemnum(7) = 0
|
||||
else mod_clk_i(1) when reg_sim_modemnum(7) = 1
|
||||
else mod_clk_i(2) when reg_sim_modemnum(7) = 2
|
||||
else mod_clk_i(3) when reg_sim_modemnum(7) = 3
|
||||
else mod_clk_i(4) when reg_sim_modemnum(7) = 4
|
||||
else mod_clk_i(5) when reg_sim_modemnum(7) = 5
|
||||
else mod_clk_i(6) when reg_sim_modemnum(7) = 6
|
||||
else mod_clk_i(7) when reg_sim_modemnum(7) = 7
|
||||
else 'Z';
|
||||
|
||||
-- Switch SIM DETECT line of SIM according to connected MODEM,
|
||||
mod_detect_o(0) <= sim_detect_i(0) when reg_sim_modemnum(0) = 0
|
||||
else sim_detect_i(1) when reg_sim_modemnum(1) = 0
|
||||
else sim_detect_i(2) when reg_sim_modemnum(2) = 0
|
||||
else sim_detect_i(3) when reg_sim_modemnum(3) = 0
|
||||
else sim_detect_i(4) when reg_sim_modemnum(4) = 0
|
||||
else sim_detect_i(5) when reg_sim_modemnum(5) = 0
|
||||
else sim_detect_i(6) when reg_sim_modemnum(6) = 0
|
||||
else sim_detect_i(7) when reg_sim_modemnum(7) = 0
|
||||
else 'Z';
|
||||
mod_detect_o(1) <= sim_detect_i(0) when reg_sim_modemnum(0) = 1
|
||||
else sim_detect_i(1) when reg_sim_modemnum(1) = 1
|
||||
else sim_detect_i(2) when reg_sim_modemnum(2) = 1
|
||||
else sim_detect_i(3) when reg_sim_modemnum(3) = 1
|
||||
else sim_detect_i(4) when reg_sim_modemnum(4) = 1
|
||||
else sim_detect_i(5) when reg_sim_modemnum(5) = 1
|
||||
else sim_detect_i(6) when reg_sim_modemnum(6) = 1
|
||||
else sim_detect_i(7) when reg_sim_modemnum(7) = 1
|
||||
else 'Z';
|
||||
mod_detect_o(2) <= sim_detect_i(0) when reg_sim_modemnum(0) = 2
|
||||
else sim_detect_i(1) when reg_sim_modemnum(1) = 2
|
||||
else sim_detect_i(2) when reg_sim_modemnum(2) = 2
|
||||
else sim_detect_i(3) when reg_sim_modemnum(3) = 2
|
||||
else sim_detect_i(4) when reg_sim_modemnum(4) = 2
|
||||
else sim_detect_i(5) when reg_sim_modemnum(5) = 2
|
||||
else sim_detect_i(6) when reg_sim_modemnum(6) = 2
|
||||
else sim_detect_i(7) when reg_sim_modemnum(7) = 2
|
||||
else 'Z';
|
||||
mod_detect_o(3) <= sim_detect_i(0) when reg_sim_modemnum(0) = 3
|
||||
else sim_detect_i(1) when reg_sim_modemnum(1) = 3
|
||||
else sim_detect_i(2) when reg_sim_modemnum(2) = 3
|
||||
else sim_detect_i(3) when reg_sim_modemnum(3) = 3
|
||||
else sim_detect_i(4) when reg_sim_modemnum(4) = 3
|
||||
else sim_detect_i(5) when reg_sim_modemnum(5) = 3
|
||||
else sim_detect_i(6) when reg_sim_modemnum(6) = 3
|
||||
else sim_detect_i(7) when reg_sim_modemnum(7) = 3
|
||||
else 'Z';
|
||||
|
||||
-- Route one-way signals from mod to SIM
|
||||
sim_pwron_o <= (others => '1');--mod_pwron_i;
|
||||
--mod_detect_o(3 downto 0) <= sim_detect_i(3 downto 0); --!! Switching
|
||||
|
||||
-- Bidir sinals routing
|
||||
gen_datalines: for i in 0 to 7 generate
|
||||
|
|
@ -204,8 +588,8 @@ begin
|
|||
s_mod_data_i(i) <= mod_data_io(i);
|
||||
mod_data_io(i) <= '0' when s_mod_data_o(i) = '0' else 'Z';
|
||||
|
||||
sim_rst_o(i) <= mod_rst_i(i);
|
||||
sim_clk_o(i) <= mod_clk_i(i);
|
||||
--sim_rst_o(i) <= mod_rst_i(i); --!! Switching
|
||||
--sim_clk_o(i) <= mod_clk_i(i); --!! Switching
|
||||
|
||||
-- Debounce data lines
|
||||
mod_dat_i_debounce : debounce
|
||||
|
|
@ -229,46 +613,188 @@ begin
|
|||
);
|
||||
end generate gen_datalines;
|
||||
|
||||
-- Route one-way signals from mod to SIM
|
||||
sim_pwron_o <= (others => '1');--mod_pwron_i;
|
||||
mod_detect_o(3 downto 0) <= sim_detect_i(3 downto 0);
|
||||
sw_mod_data_i(0) <= sdb_mod_data_i(0) when reg_sim_modemnum(0) = 0
|
||||
else sdb_mod_data_i(1) when reg_sim_modemnum(0) = 1
|
||||
else sdb_mod_data_i(2) when reg_sim_modemnum(0) = 2
|
||||
else sdb_mod_data_i(3) when reg_sim_modemnum(0) = 3
|
||||
else sdb_mod_data_i(4) when reg_sim_modemnum(0) = 4
|
||||
else sdb_mod_data_i(5) when reg_sim_modemnum(0) = 5
|
||||
else sdb_mod_data_i(6) when reg_sim_modemnum(0) = 6
|
||||
else sdb_mod_data_i(7) when reg_sim_modemnum(0) = 7
|
||||
else 'Z';
|
||||
sw_mod_data_i(1) <= sdb_mod_data_i(0) when reg_sim_modemnum(1) = 0
|
||||
else sdb_mod_data_i(1) when reg_sim_modemnum(1) = 1
|
||||
else sdb_mod_data_i(2) when reg_sim_modemnum(1) = 2
|
||||
else sdb_mod_data_i(3) when reg_sim_modemnum(1) = 3
|
||||
else sdb_mod_data_i(4) when reg_sim_modemnum(1) = 4
|
||||
else sdb_mod_data_i(5) when reg_sim_modemnum(1) = 5
|
||||
else sdb_mod_data_i(6) when reg_sim_modemnum(1) = 6
|
||||
else sdb_mod_data_i(7) when reg_sim_modemnum(1) = 7
|
||||
else 'Z';
|
||||
sw_mod_data_i(2) <= sdb_mod_data_i(0) when reg_sim_modemnum(2) = 0
|
||||
else sdb_mod_data_i(1) when reg_sim_modemnum(2) = 1
|
||||
else sdb_mod_data_i(2) when reg_sim_modemnum(2) = 2
|
||||
else sdb_mod_data_i(3) when reg_sim_modemnum(2) = 3
|
||||
else sdb_mod_data_i(4) when reg_sim_modemnum(2) = 4
|
||||
else sdb_mod_data_i(5) when reg_sim_modemnum(2) = 5
|
||||
else sdb_mod_data_i(6) when reg_sim_modemnum(2) = 6
|
||||
else sdb_mod_data_i(7) when reg_sim_modemnum(2) = 7
|
||||
else 'Z';
|
||||
sw_mod_data_i(3) <= sdb_mod_data_i(0) when reg_sim_modemnum(3) = 0
|
||||
else sdb_mod_data_i(1) when reg_sim_modemnum(3) = 1
|
||||
else sdb_mod_data_i(2) when reg_sim_modemnum(3) = 2
|
||||
else sdb_mod_data_i(3) when reg_sim_modemnum(3) = 3
|
||||
else sdb_mod_data_i(4) when reg_sim_modemnum(3) = 4
|
||||
else sdb_mod_data_i(5) when reg_sim_modemnum(3) = 5
|
||||
else sdb_mod_data_i(6) when reg_sim_modemnum(3) = 6
|
||||
else sdb_mod_data_i(7) when reg_sim_modemnum(3) = 7
|
||||
else 'Z';
|
||||
sw_mod_data_i(4) <= sdb_mod_data_i(0) when reg_sim_modemnum(4) = 0
|
||||
else sdb_mod_data_i(1) when reg_sim_modemnum(4) = 1
|
||||
else sdb_mod_data_i(2) when reg_sim_modemnum(4) = 2
|
||||
else sdb_mod_data_i(3) when reg_sim_modemnum(4) = 3
|
||||
else sdb_mod_data_i(4) when reg_sim_modemnum(4) = 4
|
||||
else sdb_mod_data_i(5) when reg_sim_modemnum(4) = 5
|
||||
else sdb_mod_data_i(6) when reg_sim_modemnum(4) = 6
|
||||
else sdb_mod_data_i(7) when reg_sim_modemnum(4) = 7
|
||||
else 'Z';
|
||||
sw_mod_data_i(5) <= sdb_mod_data_i(0) when reg_sim_modemnum(5) = 0
|
||||
else sdb_mod_data_i(1) when reg_sim_modemnum(5) = 1
|
||||
else sdb_mod_data_i(2) when reg_sim_modemnum(5) = 2
|
||||
else sdb_mod_data_i(3) when reg_sim_modemnum(5) = 3
|
||||
else sdb_mod_data_i(4) when reg_sim_modemnum(5) = 4
|
||||
else sdb_mod_data_i(5) when reg_sim_modemnum(5) = 5
|
||||
else sdb_mod_data_i(6) when reg_sim_modemnum(5) = 6
|
||||
else sdb_mod_data_i(7) when reg_sim_modemnum(5) = 7
|
||||
else 'Z';
|
||||
sw_mod_data_i(6) <= sdb_mod_data_i(0) when reg_sim_modemnum(6) = 0
|
||||
else sdb_mod_data_i(1) when reg_sim_modemnum(6) = 1
|
||||
else sdb_mod_data_i(2) when reg_sim_modemnum(6) = 2
|
||||
else sdb_mod_data_i(3) when reg_sim_modemnum(6) = 3
|
||||
else sdb_mod_data_i(4) when reg_sim_modemnum(6) = 4
|
||||
else sdb_mod_data_i(5) when reg_sim_modemnum(6) = 5
|
||||
else sdb_mod_data_i(6) when reg_sim_modemnum(6) = 6
|
||||
else sdb_mod_data_i(7) when reg_sim_modemnum(6) = 7
|
||||
else 'Z';
|
||||
sw_mod_data_i(7) <= sdb_mod_data_i(0) when reg_sim_modemnum(7) = 0
|
||||
else sdb_mod_data_i(1) when reg_sim_modemnum(7) = 1
|
||||
else sdb_mod_data_i(2) when reg_sim_modemnum(7) = 2
|
||||
else sdb_mod_data_i(3) when reg_sim_modemnum(7) = 3
|
||||
else sdb_mod_data_i(4) when reg_sim_modemnum(7) = 4
|
||||
else sdb_mod_data_i(5) when reg_sim_modemnum(7) = 5
|
||||
else sdb_mod_data_i(6) when reg_sim_modemnum(7) = 6
|
||||
else sdb_mod_data_i(7) when reg_sim_modemnum(7) = 7
|
||||
else 'Z';
|
||||
|
||||
s_mod_data_o(0) <= sw_mod_data_o(0) when reg_sim_modemnum(0) = 0
|
||||
else sw_mod_data_o(1) when reg_sim_modemnum(1) = 0
|
||||
else sw_mod_data_o(2) when reg_sim_modemnum(2) = 0
|
||||
else sw_mod_data_o(3) when reg_sim_modemnum(3) = 0
|
||||
else sw_mod_data_o(4) when reg_sim_modemnum(4) = 0
|
||||
else sw_mod_data_o(5) when reg_sim_modemnum(5) = 0
|
||||
else sw_mod_data_o(6) when reg_sim_modemnum(6) = 0
|
||||
else sw_mod_data_o(7) when reg_sim_modemnum(7) = 0
|
||||
else 'Z';
|
||||
s_mod_data_o(1) <= sw_mod_data_o(0) when reg_sim_modemnum(0) = 1
|
||||
else sw_mod_data_o(1) when reg_sim_modemnum(1) = 1
|
||||
else sw_mod_data_o(2) when reg_sim_modemnum(2) = 1
|
||||
else sw_mod_data_o(3) when reg_sim_modemnum(3) = 1
|
||||
else sw_mod_data_o(4) when reg_sim_modemnum(4) = 1
|
||||
else sw_mod_data_o(5) when reg_sim_modemnum(5) = 1
|
||||
else sw_mod_data_o(6) when reg_sim_modemnum(6) = 1
|
||||
else sw_mod_data_o(7) when reg_sim_modemnum(7) = 1
|
||||
else 'Z';
|
||||
s_mod_data_o(2) <= sw_mod_data_o(0) when reg_sim_modemnum(0) = 2
|
||||
else sw_mod_data_o(1) when reg_sim_modemnum(1) = 2
|
||||
else sw_mod_data_o(2) when reg_sim_modemnum(2) = 2
|
||||
else sw_mod_data_o(3) when reg_sim_modemnum(3) = 2
|
||||
else sw_mod_data_o(4) when reg_sim_modemnum(4) = 2
|
||||
else sw_mod_data_o(5) when reg_sim_modemnum(5) = 2
|
||||
else sw_mod_data_o(6) when reg_sim_modemnum(6) = 2
|
||||
else sw_mod_data_o(7) when reg_sim_modemnum(7) = 2
|
||||
else 'Z';
|
||||
s_mod_data_o(3) <= sw_mod_data_o(0) when reg_sim_modemnum(0) = 3
|
||||
else sw_mod_data_o(1) when reg_sim_modemnum(1) = 3
|
||||
else sw_mod_data_o(2) when reg_sim_modemnum(2) = 3
|
||||
else sw_mod_data_o(3) when reg_sim_modemnum(3) = 3
|
||||
else sw_mod_data_o(4) when reg_sim_modemnum(4) = 3
|
||||
else sw_mod_data_o(5) when reg_sim_modemnum(5) = 3
|
||||
else sw_mod_data_o(6) when reg_sim_modemnum(6) = 3
|
||||
else sw_mod_data_o(7) when reg_sim_modemnum(7) = 3
|
||||
else 'Z';
|
||||
s_mod_data_o(4) <= sw_mod_data_o(0) when reg_sim_modemnum(0) = 4
|
||||
else sw_mod_data_o(1) when reg_sim_modemnum(1) = 4
|
||||
else sw_mod_data_o(2) when reg_sim_modemnum(2) = 4
|
||||
else sw_mod_data_o(3) when reg_sim_modemnum(3) = 4
|
||||
else sw_mod_data_o(4) when reg_sim_modemnum(4) = 4
|
||||
else sw_mod_data_o(5) when reg_sim_modemnum(5) = 4
|
||||
else sw_mod_data_o(6) when reg_sim_modemnum(6) = 4
|
||||
else sw_mod_data_o(7) when reg_sim_modemnum(7) = 4
|
||||
else 'Z';
|
||||
s_mod_data_o(5) <= sw_mod_data_o(0) when reg_sim_modemnum(0) = 5
|
||||
else sw_mod_data_o(1) when reg_sim_modemnum(1) = 5
|
||||
else sw_mod_data_o(2) when reg_sim_modemnum(2) = 5
|
||||
else sw_mod_data_o(3) when reg_sim_modemnum(3) = 5
|
||||
else sw_mod_data_o(4) when reg_sim_modemnum(4) = 5
|
||||
else sw_mod_data_o(5) when reg_sim_modemnum(5) = 5
|
||||
else sw_mod_data_o(6) when reg_sim_modemnum(6) = 5
|
||||
else sw_mod_data_o(7) when reg_sim_modemnum(7) = 5
|
||||
else 'Z';
|
||||
s_mod_data_o(6) <= sw_mod_data_o(0) when reg_sim_modemnum(0) = 6
|
||||
else sw_mod_data_o(1) when reg_sim_modemnum(1) = 6
|
||||
else sw_mod_data_o(2) when reg_sim_modemnum(2) = 6
|
||||
else sw_mod_data_o(3) when reg_sim_modemnum(3) = 6
|
||||
else sw_mod_data_o(4) when reg_sim_modemnum(4) = 6
|
||||
else sw_mod_data_o(5) when reg_sim_modemnum(5) = 6
|
||||
else sw_mod_data_o(6) when reg_sim_modemnum(6) = 6
|
||||
else sw_mod_data_o(7) when reg_sim_modemnum(7) = 6
|
||||
else 'Z';
|
||||
s_mod_data_o(7) <= sw_mod_data_o(0) when reg_sim_modemnum(0) = 7
|
||||
else sw_mod_data_o(1) when reg_sim_modemnum(1) = 7
|
||||
else sw_mod_data_o(2) when reg_sim_modemnum(2) = 7
|
||||
else sw_mod_data_o(3) when reg_sim_modemnum(3) = 7
|
||||
else sw_mod_data_o(4) when reg_sim_modemnum(4) = 7
|
||||
else sw_mod_data_o(5) when reg_sim_modemnum(5) = 7
|
||||
else sw_mod_data_o(6) when reg_sim_modemnum(6) = 7
|
||||
else sw_mod_data_o(7) when reg_sim_modemnum(7) = 7
|
||||
else 'Z';
|
||||
|
||||
------------------
|
||||
-- SIM repeater --
|
||||
------------------
|
||||
sim_rptr_proc: process(clk25_i, s_rstn_i, sdb_sim_data_i, sdb_sim_data_prev, sdb_mod_data_i, sdb_mod_data_prev) is
|
||||
sim_rptr_proc: process(clk25_i, s_rstn_i, sdb_sim_data_i, sdb_sim_data_prev, sw_mod_data_i, sw_mod_data_prev, reg_sim_change_irq) is
|
||||
begin
|
||||
if s_rstn_i = '0' then
|
||||
s_sim_data_o <= (others => '1');
|
||||
s_mod_data_o <= (others => '1');
|
||||
sw_mod_data_o <= (others => '1');
|
||||
sdb_sim_data_prev <= sdb_sim_data_i;
|
||||
sdb_mod_data_prev <= sdb_mod_data_i;
|
||||
sw_mod_data_prev <= sw_mod_data_i;
|
||||
state <= (others => idle);
|
||||
|
||||
elsif (rising_edge(clk25_i)) then
|
||||
sdb_sim_data_prev <= sdb_sim_data_i;
|
||||
sdb_mod_data_prev <= sdb_mod_data_i;
|
||||
sw_mod_data_prev <= sw_mod_data_i;
|
||||
|
||||
for i in 0 to 7 loop
|
||||
case state(i) is
|
||||
when idle =>
|
||||
if (sdb_mod_data_prev(i) = '1' and sdb_mod_data_i(i) = '0') then
|
||||
if (sw_mod_data_prev(i) = '1' and sw_mod_data_i(i) = '0') then
|
||||
s_sim_data_o(i) <= '0';
|
||||
state(i) <= mod_to_sim;
|
||||
elsif (sdb_sim_data_prev(i) = '1' and sdb_sim_data_i(i) = '0') then
|
||||
s_mod_data_o(i) <= '0';
|
||||
sw_mod_data_o(i) <= '0';
|
||||
state(i) <= sim_to_mod;
|
||||
end if;
|
||||
|
||||
when mod_to_sim =>
|
||||
if (sdb_mod_data_prev(i) = '0' and sdb_mod_data_i(i) = '1') then
|
||||
if ((sw_mod_data_prev(i) = '0' and sw_mod_data_i(i) = '1') or reg_sim_change_irq(i) = '1') then
|
||||
s_sim_data_o(i) <= '1';
|
||||
state(i) <= idle;
|
||||
end if;
|
||||
|
||||
when sim_to_mod =>
|
||||
if (sdb_sim_data_prev(i) = '0' and sdb_sim_data_i(i) = '1') then
|
||||
s_mod_data_o(i) <= '1';
|
||||
if ((sdb_sim_data_prev(i) = '0' and sdb_sim_data_i(i) = '1') or reg_sim_change_irq(i) = '1') then
|
||||
sw_mod_data_o(i) <= '1';
|
||||
state(i) <= idle;
|
||||
end if;
|
||||
end case;
|
||||
|
|
|
|||
Loading…
Reference in New Issue