302 lines
10 KiB
VHDL
302 lines
10 KiB
VHDL
------------------------------------------------------------
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-- File : I2C_slave.vhd
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------------------------------------------------------------
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-- Author : Peter Samarin <peter.samarin@gmail.com>
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------------------------------------------------------------
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-- Copyright (c) 2016 Peter Samarin
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------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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------------------------------------------------------------
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entity i2c_slave is
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generic (
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SLAVE_ADDR : std_logic_vector(6 downto 0));
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port (
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scl : inout std_logic;
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sda : inout std_logic;
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clk : in std_logic;
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rst : in std_logic;
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-- User interface
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read_req : out std_logic;
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data_to_master : in std_logic_vector(7 downto 0);
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data_valid : out std_logic;
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data_from_master : out std_logic_vector(7 downto 0));
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end entity i2c_slave;
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------------------------------------------------------------
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architecture arch of i2c_slave is
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-- this assumes that system's clock is much faster than SCL
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constant DEBOUNCING_WAIT_CYCLES : integer := 4;
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type state_t is (idle, get_address_and_cmd,
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answer_ack_start, write,
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read, read_ack_start,
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read_ack_got_rising, read_stop);
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-- I2C state management
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signal state_reg : state_t := idle;
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signal cmd_reg : std_logic := '0';
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signal bits_processed_reg : integer range 0 to 8 := 0;
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signal continue_reg : std_logic := '0';
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signal scl_reg : std_logic := '1';
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signal sda_reg : std_logic := '1';
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signal scl_debounced : std_logic := '1';
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signal sda_debounced : std_logic := '1';
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-- Helpers to figure out next state
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signal start_reg : std_logic := '0';
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signal stop_reg : std_logic := '0';
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signal scl_rising_reg : std_logic := '0';
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signal scl_falling_reg : std_logic := '0';
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-- Address and data received from master
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signal addr_reg : std_logic_vector(6 downto 0) := (others => '0');
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signal data_reg : std_logic_vector(6 downto 0) := (others => '0');
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signal data_from_master_reg : std_logic_vector(7 downto 0) := (others => '0');
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signal scl_prev_reg : std_logic := '1';
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-- Slave writes on scl
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signal scl_wen_reg : std_logic := '0';
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signal scl_o_reg : std_logic := '0';
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signal sda_prev_reg : std_logic := '1';
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-- Slave writes on sda
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signal sda_wen_reg : std_logic := '0';
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signal sda_o_reg : std_logic := '0';
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-- User interface
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signal data_valid_reg : std_logic := '0';
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signal read_req_reg : std_logic := '0';
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signal data_to_master_reg : std_logic_vector(7 downto 0) := (others => '0');
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begin
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-- debounce SCL and SDA
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SCL_debounce : entity work.debounce
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generic map (
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WAIT_CYCLES => DEBOUNCING_WAIT_CYCLES)
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port map (
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clk => clk,
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signal_in => scl_reg,
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signal_out => scl_debounced);
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-- it might not make sense to debounce SDA, since master
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-- and slave can both write to it...
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SDA_debounce : entity work.debounce
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generic map (
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WAIT_CYCLES => DEBOUNCING_WAIT_CYCLES)
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port map (
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clk => clk,
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signal_in => sda_reg,
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signal_out => sda_debounced);
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process (clk) is
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begin
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if rising_edge(clk) then
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-- save SCL in registers that are used for debouncing
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scl_reg <= scl;
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sda_reg <= sda;
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-- Delay debounced SCL and SDA by 1 clock cycle
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scl_prev_reg <= scl_debounced;
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sda_prev_reg <= sda_debounced;
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-- Detect rising and falling SCL
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scl_rising_reg <= '0';
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if scl_prev_reg = '0' and scl_debounced = '1' then
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scl_rising_reg <= '1';
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end if;
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scl_falling_reg <= '0';
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if scl_prev_reg = '1' and scl_debounced = '0' then
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scl_falling_reg <= '1';
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end if;
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-- Detect I2C START condition
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start_reg <= '0';
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stop_reg <= '0';
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if scl_debounced = '1' and scl_prev_reg = '1' and
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sda_prev_reg = '1' and sda_debounced = '0' then
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start_reg <= '1';
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stop_reg <= '0';
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end if;
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-- Detect I2C STOP condition
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if scl_prev_reg = '1' and scl_debounced = '1' and
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sda_prev_reg = '0' and sda_debounced = '1' then
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start_reg <= '0';
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stop_reg <= '1';
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end if;
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end if;
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end process;
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----------------------------------------------------------
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-- I2C state machine
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----------------------------------------------------------
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process (clk) is
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begin
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if rising_edge(clk) then
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-- Default assignments
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sda_o_reg <= '0';
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sda_wen_reg <= '0';
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-- User interface
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data_valid_reg <= '0';
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read_req_reg <= '0';
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case state_reg is
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when idle =>
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if start_reg = '1' then
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state_reg <= get_address_and_cmd;
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bits_processed_reg <= 0;
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end if;
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when get_address_and_cmd =>
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if scl_rising_reg = '1' then
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if bits_processed_reg < 7 then
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bits_processed_reg <= bits_processed_reg + 1;
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addr_reg(6-bits_processed_reg) <= sda_debounced;
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elsif bits_processed_reg = 7 then
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bits_processed_reg <= bits_processed_reg + 1;
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cmd_reg <= sda_debounced;
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end if;
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end if;
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if bits_processed_reg = 8 and scl_falling_reg = '1' then
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bits_processed_reg <= 0;
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if addr_reg = SLAVE_ADDR then -- check req address
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state_reg <= answer_ack_start;
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if cmd_reg = '1' then -- issue read request
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read_req_reg <= '1';
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data_to_master_reg <= data_to_master;
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end if;
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else
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assert false
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report ("I2C: target/slave address mismatch (data is being sent to another slave).")
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severity note;
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state_reg <= idle;
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end if;
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end if;
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----------------------------------------------------
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-- I2C acknowledge to master
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----------------------------------------------------
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when answer_ack_start =>
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sda_wen_reg <= '1';
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sda_o_reg <= '0';
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if scl_falling_reg = '1' then
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if cmd_reg = '0' then
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state_reg <= write;
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else
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state_reg <= read;
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end if;
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end if;
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----------------------------------------------------
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-- WRITE
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----------------------------------------------------
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when write =>
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if scl_rising_reg = '1' then
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bits_processed_reg <= bits_processed_reg + 1;
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if bits_processed_reg < 7 then
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data_reg(6-bits_processed_reg) <= sda_debounced;
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else
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data_from_master_reg <= data_reg & sda_debounced;
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data_valid_reg <= '1';
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end if;
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end if;
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if scl_falling_reg = '1' and bits_processed_reg = 8 then
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state_reg <= answer_ack_start;
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bits_processed_reg <= 0;
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end if;
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----------------------------------------------------
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-- READ: send data to master
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----------------------------------------------------
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when read =>
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sda_wen_reg <= '1';
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sda_o_reg <= data_to_master_reg(7-bits_processed_reg);
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if scl_falling_reg = '1' then
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if bits_processed_reg < 7 then
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bits_processed_reg <= bits_processed_reg + 1;
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elsif bits_processed_reg = 7 then
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state_reg <= read_ack_start;
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bits_processed_reg <= 0;
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end if;
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end if;
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----------------------------------------------------
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-- I2C read master acknowledge
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----------------------------------------------------
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when read_ack_start =>
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if scl_rising_reg = '1' then
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state_reg <= read_ack_got_rising;
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if sda_debounced = '1' then -- nack = stop read
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continue_reg <= '0';
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else -- ack = continue read
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continue_reg <= '1';
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read_req_reg <= '1'; -- request reg byte
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data_to_master_reg <= data_to_master;
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end if;
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end if;
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when read_ack_got_rising =>
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if scl_falling_reg = '1' then
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if continue_reg = '1' then
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if cmd_reg = '0' then
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state_reg <= write;
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else
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state_reg <= read;
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end if;
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else
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state_reg <= read_stop;
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end if;
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end if;
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-- Wait for START or STOP to get out of this state
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when read_stop =>
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null;
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-- Wait for START or STOP to get out of this state
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when others =>
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assert false
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report ("I2C: error: ended in an impossible state.")
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severity error;
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state_reg <= idle;
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end case;
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--------------------------------------------------------
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-- Reset counter and state on start/stop
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--------------------------------------------------------
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if start_reg = '1' then
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state_reg <= get_address_and_cmd;
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bits_processed_reg <= 0;
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end if;
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if stop_reg = '1' then
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state_reg <= idle;
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bits_processed_reg <= 0;
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end if;
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if rst = '1' then
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state_reg <= idle;
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end if;
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end if;
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end process;
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----------------------------------------------------------
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-- I2C interface
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----------------------------------------------------------
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sda <= sda_o_reg when sda_wen_reg = '1' else
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'Z';
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scl <= scl_o_reg when scl_wen_reg = '1' else
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'Z';
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----------------------------------------------------------
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-- User interface
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----------------------------------------------------------
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-- Master writes
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data_valid <= data_valid_reg;
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data_from_master <= data_from_master_reg;
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-- Master reads
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read_req <= read_req_reg;
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end architecture arch;
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