SmartSwitchESP32/include/rtl8370/rtk_api.h

#ifndef __RTK_API_H__
#define __RTK_API_H__

/*
 * Include Files
 */
#include <rtk_types.h>
#include <rtk_error.h>

/*
 * Data Type Declaration
 */
#define ENABLE 1
#define DISABLE 0

#define PHY_CONTROL_REG 0
#define PHY_STATUS_REG 1
#define PHY_AN_ADVERTISEMENT_REG 4
#define PHY_AN_LINKPARTNER_REG 5
#define PHY_1000_BASET_CONTROL_REG 9
#define PHY_1000_BASET_STATUS_REG 10
#define PHY_RESOLVED_REG 17
#define PHY_POWERSAVING_REG 21
#define PHY_POWERSAVING_OFFSET 12
#define PHY_POWERSAVING_MASK 0x1000
#define PHY_PAGE_ADDRESS 31

/*Qos related configuration define*/
#define QOS_DEFAULT_TICK_PERIOD (19 - 1)
#define QOS_DEFAULT_BYTE_PER_TOKEN 34
#define QOS_DEFAULT_LK_THRESHOLD (34 * 3) /* Why use 0x400? */

#define QOS_DEFAULT_INGRESS_BANDWIDTH 0x3FFF /* 0x3FFF => unlimit */
#define QOS_DEFAULT_EGRESS_BANDWIDTH 0x3D08  /*( 0x3D08 + 1) * 64Kbps => 1Gbps*/
#define QOS_DEFAULT_PREIFP 1
#define QOS_DEFAULT_PACKET_USED_PAGES_FC 0x60
#define QOS_DEFAULT_PACKET_USED_FC_EN 0
#define QOS_DEFAULT_QUEUE_BASED_FC_EN 1

#define QOS_DEFAULT_PRIORITY_SELECT_PORT 8
#define QOS_DEFAULT_PRIORITY_SELECT_1Q 0
#define QOS_DEFAULT_PRIORITY_SELECT_ACL 0
#define QOS_DEFAULT_PRIORITY_SELECT_DSCP 0

#define QOS_DEFAULT_DSCP_MAPPING_PRIORITY 0

#define QOS_DEFAULT_1Q_REMARKING_ABILITY 0
#define QOS_DEFAULT_DSCP_REMARKING_ABILITY 0
#define QOS_DEFAULT_QUEUE_GAP 20
#define QOS_DEFAULT_QUEUE_NO_MAX 6
#define QOS_DEFAULT_AVERAGE_PACKET_RATE 0x3FFF
#define QOS_DEFAULT_BURST_SIZE_IN_APR 0x3F
#define QOS_DEFAULT_PEAK_PACKET_RATE 2
#define QOS_DEFAULT_SCHEDULER_ABILITY_APR 1 /*disable*/
#define QOS_DEFAULT_SCHEDULER_ABILITY_PPR 1 /*disable*/
#define QOS_DEFAULT_SCHEDULER_ABILITY_WFQ 1 /*disable*/

#define QOS_WEIGHT_MAX 128

#define LED_GROUP_MAX 3

#define ACL_DEFAULT_ABILITY 0
#define ACL_DEFAULT_UNMATCH_PERMIT 1

#define ACL_RULE_FREE 0
#define ACL_RULE_INAVAILABLE 1

#define FILTER_POLICING_MAX 8
#define FILTER_LOGGING_MAX 8
#define FILTER_PATTERN_MAX 4

#define STORM_UNUC_INDEX 39
#define STORM_UNMC_INDEX 47
#define STORM_MC_INDEX 55
#define STORM_BC_INDEX 63

#define RTK_MAX_NUM_OF_INTERRUPT_TYPE 1
#define RTK_MAX_NUM_OF_LED_GROUP 3
#define RTK_TOTAL_NUM_OF_WORD_FOR_1BIT_PORT_LIST 1
#define RTK_MAX_NUM_OF_PRIORITY 8
#define RTK_MAX_NUM_OF_QUEUE 8
#define RTK_MAX_NUM_OF_TRUNK_HASH_VAL 1
#define RTK_MAX_NUM_OF_INTERRUPT_TYPE 1
#define RTK_MAX_NUM_OF_PORT 10
#define RTK_PORT_ID_MAX (RTK_MAX_NUM_OF_PORT - 1)
#define RTK_PHY_ID_MAX (RTK_MAX_NUM_OF_PORT - 3)
#define RTK_QUEUE_ID_MAX (RTK_MAX_NUM_OF_QUEUE - 1)
#define RTK_MAX_NUM_OF_PROTO_TYPE 0xFFFF
#define RTK_MAX_NUM_OF_MSTI 16
#define RTK_MAX_NUM_OF_LEARN_LIMIT 0x2040
#define RTK_MAX_PORT_MASK 0x3FF
#define RTK_MAX_INPUT_RATE (0x1FFFF * 8)
#define RTK_MIN_INPUT_RATE 8
#define RTK_RATE_GRANULARTY_UNIT 8
#define RTK_DOT1X_PAE 3
#define RTK_L2_DEFAULT_TIME 6
#define RTK_L2_DEFAULT_SPEED 2
#define RTK_MAX_NUM_OF_SVLAN_INDEX 64
#define RTK_MAX_NUM_OF_SP2C_INDEX 128
#define RTK_MAX_NUM_OF_MC2S_INDEX 32
#define RTK_MAX_NUM_OF_C2S_INDEX 128
#define RTK_VLAN_ID_MIN 0
#define RTK_VLAN_ID_MAX 4095
#define RTK_DOT1P_PRIORITY_MAX 7
#define RTK_MAX_NUM_OF_FILTER_TYPE 5
#define RTK_MAX_NUM_OF_FILTER_FIELD 7
#define RTK_MAX_NUM_OF_FILTER_PORT 16
#define RTK_MAX_NUM_OF_METER 64
#define RTK_QOS_RATE_INPUT_MAX (0x1FFFF * 8)
#define RTK_QOS_RATE_INPUT_MIN 8
#define RTK_VALUE_OF_DSCP_MAX 63
#define RTK_VALUE_OF_DSCP_MIN 0
#define RTK_EFID_MAX 0x7
#define RTK_FID_MAX 0xFFF
#define RTK_MAX_NUM_OF_VLAN_INDEX 32
#define RTK_MAX_NUM_OF_PROTOVLAN_GROUP 4
#define RTK_PROTOVLAN_GROUP_ID_MAX (RTK_MAX_NUM_OF_PROTOVLAN_GROUP - 1)
#define RTK_MAX_NUM_OF_ACL_RULE 64
#define RTK_SVLAN_TPID 0x88a8
#define RTK_PORT_TRUNK_GROUP_MASK(group) (0xF << (group << 2))
#define RTK_PORT_TRUNK_GROUP_OFFSET(group) (group << 2)

#define RTK_INDRECT_ACCESS_CRTL 0x1f00
#define RTK_INDRECT_ACCESS_STATUS 0x1f01
#define RTK_INDRECT_ACCESS_ADDRESS 0x1f02
#define RTK_INDRECT_ACCESS_WRITE_DATA 0x1f03
#define RTK_INDRECT_ACCESS_READ_DATA 0x1f04
#define RTK_INDRECT_ACCESS_DELAY 0x1f80
#define RTK_INDRECT_ACCESS_BURST 0x1f81
#define RTK_RW_MASK 0x2
#define RTK_CMD_MASK 0x1
#define RTK_PHY_BUSY_OFFSET 2

#define RTK_WHOLE_SYSTEM 0xFF

#define RTK_EXT_0 0
#define RTK_EXT_1 1

#define RTK_EXT_0_MAC 9
#define RTK_EXT_1_MAC 8

#ifndef MAC_ADDR_LEN
#define MAC_ADDR_LEN 6
#endif

#define IPV6_ADDR_LEN 16
#define IPV4_ADDR_LEN 4

#define RTK_DOT_1AS_TIMESTAMP_UNIT_IN_WORD_LENGTH 3UL

#define RTK_IPV6_ADDR_WORD_LENGTH 4UL

typedef enum rtk_cpu_insert_e
{
    CPU_INSERT_TO_ALL = 0,
    CPU_INSERT_TO_TRAPPING,
    CPU_INSERT_TO_NONE,
    CPU_INSERT_END
} rtk_cpu_insert_t;

typedef enum rtk_cpu_position_e
{
    CPU_POS_ATTER_DA = 0,
    CPU_POS_AFTER_CRC,
    CPU_POS_END
} rtk_cpu_position_t;

typedef uint32 rtk_data_t;

/* Type of port-based dot1x auth/unauth*/
typedef enum rtk_dot1x_auth_status_e
{
    UNAUTH = 0,
    AUTH,
    AUTH_STATUS_END
} rtk_dot1x_auth_status_t;

typedef enum rtk_dot1x_direction_e
{
    BOTH = 0,
    IN,
    DIRECTION_END
} rtk_dot1x_direction_t;

typedef enum rtk_mode_ext_e
{
    MODE_EXT_DISABLE = 0,
    MODE_EXT_RGMII,
    MODE_EXT_MII_MAC,
    MODE_EXT_MII_PHY,
    MODE_EXT_TMII_MAC,
    MODE_EXT_TMII_PHY,
    MODE_EXT_GMII,
    MODE_EXT_RGMII_33V,
    MODE_EXT_END
} rtk_mode_ext_t;

typedef enum rtk_led_group_e
{
    LED_GROUP_0 = 0,
    LED_GROUP_1,
    LED_GROUP_2,
    LED_GROUP_END
} rtk_led_group_t;

typedef struct rtk_port_mac_ability_s
{
    uint32 forcemode;
    uint32 speed;
    uint32 duplex;
    uint32 link;
    uint32 nway;
    uint32 txpause;
    uint32 rxpause;
    uint32 lpi100;
    uint32 lpi1000;
} rtk_port_mac_ability_t;

typedef struct rtk_portmask_s
{
    uint32 bits[RTK_TOTAL_NUM_OF_WORD_FOR_1BIT_PORT_LIST];
} rtk_portmask_t;

int RTL8370_init(void);

#endif