226 lines
5.6 KiB
C
226 lines
5.6 KiB
C
#ifndef __RTK_API_H__
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#define __RTK_API_H__
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/*
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* Include Files
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*/
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#include <rtk_types.h>
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#include <rtk_error.h>
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/*
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* Data Type Declaration
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*/
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#define ENABLE 1
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#define DISABLE 0
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#define PHY_CONTROL_REG 0
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#define PHY_STATUS_REG 1
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#define PHY_AN_ADVERTISEMENT_REG 4
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#define PHY_AN_LINKPARTNER_REG 5
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#define PHY_1000_BASET_CONTROL_REG 9
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#define PHY_1000_BASET_STATUS_REG 10
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#define PHY_RESOLVED_REG 17
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#define PHY_POWERSAVING_REG 21
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#define PHY_POWERSAVING_OFFSET 12
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#define PHY_POWERSAVING_MASK 0x1000
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#define PHY_PAGE_ADDRESS 31
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/*Qos related configuration define*/
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#define QOS_DEFAULT_TICK_PERIOD (19 - 1)
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#define QOS_DEFAULT_BYTE_PER_TOKEN 34
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#define QOS_DEFAULT_LK_THRESHOLD (34 * 3) /* Why use 0x400? */
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#define QOS_DEFAULT_INGRESS_BANDWIDTH 0x3FFF /* 0x3FFF => unlimit */
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#define QOS_DEFAULT_EGRESS_BANDWIDTH 0x3D08 /*( 0x3D08 + 1) * 64Kbps => 1Gbps*/
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#define QOS_DEFAULT_PREIFP 1
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#define QOS_DEFAULT_PACKET_USED_PAGES_FC 0x60
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#define QOS_DEFAULT_PACKET_USED_FC_EN 0
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#define QOS_DEFAULT_QUEUE_BASED_FC_EN 1
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#define QOS_DEFAULT_PRIORITY_SELECT_PORT 8
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#define QOS_DEFAULT_PRIORITY_SELECT_1Q 0
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#define QOS_DEFAULT_PRIORITY_SELECT_ACL 0
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#define QOS_DEFAULT_PRIORITY_SELECT_DSCP 0
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#define QOS_DEFAULT_DSCP_MAPPING_PRIORITY 0
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#define QOS_DEFAULT_1Q_REMARKING_ABILITY 0
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#define QOS_DEFAULT_DSCP_REMARKING_ABILITY 0
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#define QOS_DEFAULT_QUEUE_GAP 20
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#define QOS_DEFAULT_QUEUE_NO_MAX 6
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#define QOS_DEFAULT_AVERAGE_PACKET_RATE 0x3FFF
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#define QOS_DEFAULT_BURST_SIZE_IN_APR 0x3F
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#define QOS_DEFAULT_PEAK_PACKET_RATE 2
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#define QOS_DEFAULT_SCHEDULER_ABILITY_APR 1 /*disable*/
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#define QOS_DEFAULT_SCHEDULER_ABILITY_PPR 1 /*disable*/
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#define QOS_DEFAULT_SCHEDULER_ABILITY_WFQ 1 /*disable*/
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#define QOS_WEIGHT_MAX 128
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#define LED_GROUP_MAX 3
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#define ACL_DEFAULT_ABILITY 0
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#define ACL_DEFAULT_UNMATCH_PERMIT 1
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#define ACL_RULE_FREE 0
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#define ACL_RULE_INAVAILABLE 1
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#define FILTER_POLICING_MAX 8
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#define FILTER_LOGGING_MAX 8
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#define FILTER_PATTERN_MAX 4
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#define STORM_UNUC_INDEX 39
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#define STORM_UNMC_INDEX 47
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#define STORM_MC_INDEX 55
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#define STORM_BC_INDEX 63
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#define RTK_MAX_NUM_OF_INTERRUPT_TYPE 1
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#define RTK_MAX_NUM_OF_LED_GROUP 3
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#define RTK_TOTAL_NUM_OF_WORD_FOR_1BIT_PORT_LIST 1
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#define RTK_MAX_NUM_OF_PRIORITY 8
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#define RTK_MAX_NUM_OF_QUEUE 8
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#define RTK_MAX_NUM_OF_TRUNK_HASH_VAL 1
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#define RTK_MAX_NUM_OF_INTERRUPT_TYPE 1
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#define RTK_MAX_NUM_OF_PORT 10
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#define RTK_PORT_ID_MAX (RTK_MAX_NUM_OF_PORT - 1)
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#define RTK_PHY_ID_MAX (RTK_MAX_NUM_OF_PORT - 3)
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#define RTK_QUEUE_ID_MAX (RTK_MAX_NUM_OF_QUEUE - 1)
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#define RTK_MAX_NUM_OF_PROTO_TYPE 0xFFFF
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#define RTK_MAX_NUM_OF_MSTI 16
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#define RTK_MAX_NUM_OF_LEARN_LIMIT 0x2040
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#define RTK_MAX_PORT_MASK 0x3FF
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#define RTK_MAX_INPUT_RATE (0x1FFFF * 8)
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#define RTK_MIN_INPUT_RATE 8
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#define RTK_RATE_GRANULARTY_UNIT 8
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#define RTK_DOT1X_PAE 3
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#define RTK_L2_DEFAULT_TIME 6
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#define RTK_L2_DEFAULT_SPEED 2
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#define RTK_MAX_NUM_OF_SVLAN_INDEX 64
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#define RTK_MAX_NUM_OF_SP2C_INDEX 128
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#define RTK_MAX_NUM_OF_MC2S_INDEX 32
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#define RTK_MAX_NUM_OF_C2S_INDEX 128
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#define RTK_VLAN_ID_MIN 0
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#define RTK_VLAN_ID_MAX 4095
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#define RTK_DOT1P_PRIORITY_MAX 7
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#define RTK_MAX_NUM_OF_FILTER_TYPE 5
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#define RTK_MAX_NUM_OF_FILTER_FIELD 7
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#define RTK_MAX_NUM_OF_FILTER_PORT 16
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#define RTK_MAX_NUM_OF_METER 64
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#define RTK_QOS_RATE_INPUT_MAX (0x1FFFF * 8)
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#define RTK_QOS_RATE_INPUT_MIN 8
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#define RTK_VALUE_OF_DSCP_MAX 63
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#define RTK_VALUE_OF_DSCP_MIN 0
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#define RTK_EFID_MAX 0x7
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#define RTK_FID_MAX 0xFFF
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#define RTK_MAX_NUM_OF_VLAN_INDEX 32
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#define RTK_MAX_NUM_OF_PROTOVLAN_GROUP 4
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#define RTK_PROTOVLAN_GROUP_ID_MAX (RTK_MAX_NUM_OF_PROTOVLAN_GROUP - 1)
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#define RTK_MAX_NUM_OF_ACL_RULE 64
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#define RTK_SVLAN_TPID 0x88a8
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#define RTK_PORT_TRUNK_GROUP_MASK(group) (0xF << (group << 2))
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#define RTK_PORT_TRUNK_GROUP_OFFSET(group) (group << 2)
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#define RTK_INDRECT_ACCESS_CRTL 0x1f00
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#define RTK_INDRECT_ACCESS_STATUS 0x1f01
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#define RTK_INDRECT_ACCESS_ADDRESS 0x1f02
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#define RTK_INDRECT_ACCESS_WRITE_DATA 0x1f03
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#define RTK_INDRECT_ACCESS_READ_DATA 0x1f04
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#define RTK_INDRECT_ACCESS_DELAY 0x1f80
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#define RTK_INDRECT_ACCESS_BURST 0x1f81
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#define RTK_RW_MASK 0x2
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#define RTK_CMD_MASK 0x1
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#define RTK_PHY_BUSY_OFFSET 2
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#define RTK_WHOLE_SYSTEM 0xFF
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#define RTK_EXT_0 0
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#define RTK_EXT_1 1
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#define RTK_EXT_0_MAC 9
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#define RTK_EXT_1_MAC 8
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#ifndef MAC_ADDR_LEN
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#define MAC_ADDR_LEN 6
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#endif
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#define IPV6_ADDR_LEN 16
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#define IPV4_ADDR_LEN 4
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#define RTK_DOT_1AS_TIMESTAMP_UNIT_IN_WORD_LENGTH 3UL
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#define RTK_IPV6_ADDR_WORD_LENGTH 4UL
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typedef enum rtk_cpu_insert_e
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{
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CPU_INSERT_TO_ALL = 0,
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CPU_INSERT_TO_TRAPPING,
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CPU_INSERT_TO_NONE,
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CPU_INSERT_END
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} rtk_cpu_insert_t;
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typedef enum rtk_cpu_position_e
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{
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CPU_POS_ATTER_DA = 0,
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CPU_POS_AFTER_CRC,
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CPU_POS_END
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} rtk_cpu_position_t;
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typedef uint32 rtk_data_t;
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/* Type of port-based dot1x auth/unauth*/
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typedef enum rtk_dot1x_auth_status_e
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{
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UNAUTH = 0,
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AUTH,
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AUTH_STATUS_END
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} rtk_dot1x_auth_status_t;
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typedef enum rtk_dot1x_direction_e
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{
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BOTH = 0,
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IN,
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DIRECTION_END
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} rtk_dot1x_direction_t;
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typedef enum rtk_mode_ext_e
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{
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MODE_EXT_DISABLE = 0,
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MODE_EXT_RGMII,
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MODE_EXT_MII_MAC,
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MODE_EXT_MII_PHY,
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MODE_EXT_TMII_MAC,
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MODE_EXT_TMII_PHY,
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MODE_EXT_GMII,
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MODE_EXT_RGMII_33V,
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MODE_EXT_END
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} rtk_mode_ext_t;
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typedef enum rtk_led_group_e
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{
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LED_GROUP_0 = 0,
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LED_GROUP_1,
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LED_GROUP_2,
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LED_GROUP_END
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} rtk_led_group_t;
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typedef struct rtk_port_mac_ability_s
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{
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uint32 forcemode;
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uint32 speed;
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uint32 duplex;
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uint32 link;
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uint32 nway;
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uint32 txpause;
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uint32 rxpause;
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uint32 lpi100;
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uint32 lpi1000;
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} rtk_port_mac_ability_t;
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typedef struct rtk_portmask_s
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{
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uint32 bits[RTK_TOTAL_NUM_OF_WORD_FOR_1BIT_PORT_LIST];
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} rtk_portmask_t;
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int RTL8370_init(void);
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#endif |