Initial commit
This commit is contained in:
Sergey Biryukov
commit
8662ab79d9
|
|
@ -0,0 +1,5 @@
|
|||
.pio
|
||||
.vscode/.browse.c_cpp.db*
|
||||
.vscode/c_cpp_properties.json
|
||||
.vscode/launch.json
|
||||
.vscode/ipch
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
{
|
||||
// See http://go.microsoft.com/fwlink/?LinkId=827846
|
||||
// for the documentation about the extensions.json format
|
||||
"recommendations": [
|
||||
"platformio.platformio-ide"
|
||||
],
|
||||
"unwantedRecommendations": [
|
||||
"ms-vscode.cpptools-extension-pack"
|
||||
]
|
||||
}
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
|
||||
This directory is intended for project header files.
|
||||
|
||||
A header file is a file containing C declarations and macro definitions
|
||||
to be shared between several project source files. You request the use of a
|
||||
header file in your project source file (C, C++, etc) located in `src` folder
|
||||
by including it, with the C preprocessing directive `#include'.
|
||||
|
||||
```src/main.c
|
||||
|
||||
#include "header.h"
|
||||
|
||||
int main (void)
|
||||
{
|
||||
...
|
||||
}
|
||||
```
|
||||
|
||||
Including a header file produces the same results as copying the header file
|
||||
into each source file that needs it. Such copying would be time-consuming
|
||||
and error-prone. With a header file, the related declarations appear
|
||||
in only one place. If they need to be changed, they can be changed in one
|
||||
place, and programs that include the header file will automatically use the
|
||||
new version when next recompiled. The header file eliminates the labor of
|
||||
finding and changing all the copies as well as the risk that a failure to
|
||||
find one copy will result in inconsistencies within a program.
|
||||
|
||||
In C, the usual convention is to give header files names that end with `.h'.
|
||||
It is most portable to use only letters, digits, dashes, and underscores in
|
||||
header file names, and at most one dot.
|
||||
|
||||
Read more about using header files in official GCC documentation:
|
||||
|
||||
* Include Syntax
|
||||
* Include Operation
|
||||
* Once-Only Headers
|
||||
* Computed Includes
|
||||
|
||||
https://gcc.gnu.org/onlinedocs/cpp/Header-Files.html
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
|
||||
#define BLUE_LED 21
|
||||
|
||||
#define SWITCH_RESET GPIO_NUM_25
|
||||
#define SWITCH_CLK GPIO_NUM_26
|
||||
#define SWITCH_DATA GPIO_NUM_27
|
||||
|
||||
#define SWITCH_ADDR 0x5C
|
||||
|
|
@ -0,0 +1,226 @@
|
|||
#ifndef __RTK_API_H__
|
||||
#define __RTK_API_H__
|
||||
|
||||
/*
|
||||
* Include Files
|
||||
*/
|
||||
#include <rtk_types.h>
|
||||
#include <rtk_error.h>
|
||||
|
||||
/*
|
||||
* Data Type Declaration
|
||||
*/
|
||||
#define ENABLE 1
|
||||
#define DISABLE 0
|
||||
|
||||
#define PHY_CONTROL_REG 0
|
||||
#define PHY_STATUS_REG 1
|
||||
#define PHY_AN_ADVERTISEMENT_REG 4
|
||||
#define PHY_AN_LINKPARTNER_REG 5
|
||||
#define PHY_1000_BASET_CONTROL_REG 9
|
||||
#define PHY_1000_BASET_STATUS_REG 10
|
||||
#define PHY_RESOLVED_REG 17
|
||||
#define PHY_POWERSAVING_REG 21
|
||||
#define PHY_POWERSAVING_OFFSET 12
|
||||
#define PHY_POWERSAVING_MASK 0x1000
|
||||
#define PHY_PAGE_ADDRESS 31
|
||||
|
||||
/*Qos related configuration define*/
|
||||
#define QOS_DEFAULT_TICK_PERIOD (19 - 1)
|
||||
#define QOS_DEFAULT_BYTE_PER_TOKEN 34
|
||||
#define QOS_DEFAULT_LK_THRESHOLD (34 * 3) /* Why use 0x400? */
|
||||
|
||||
#define QOS_DEFAULT_INGRESS_BANDWIDTH 0x3FFF /* 0x3FFF => unlimit */
|
||||
#define QOS_DEFAULT_EGRESS_BANDWIDTH 0x3D08 /*( 0x3D08 + 1) * 64Kbps => 1Gbps*/
|
||||
#define QOS_DEFAULT_PREIFP 1
|
||||
#define QOS_DEFAULT_PACKET_USED_PAGES_FC 0x60
|
||||
#define QOS_DEFAULT_PACKET_USED_FC_EN 0
|
||||
#define QOS_DEFAULT_QUEUE_BASED_FC_EN 1
|
||||
|
||||
#define QOS_DEFAULT_PRIORITY_SELECT_PORT 8
|
||||
#define QOS_DEFAULT_PRIORITY_SELECT_1Q 0
|
||||
#define QOS_DEFAULT_PRIORITY_SELECT_ACL 0
|
||||
#define QOS_DEFAULT_PRIORITY_SELECT_DSCP 0
|
||||
|
||||
#define QOS_DEFAULT_DSCP_MAPPING_PRIORITY 0
|
||||
|
||||
#define QOS_DEFAULT_1Q_REMARKING_ABILITY 0
|
||||
#define QOS_DEFAULT_DSCP_REMARKING_ABILITY 0
|
||||
#define QOS_DEFAULT_QUEUE_GAP 20
|
||||
#define QOS_DEFAULT_QUEUE_NO_MAX 6
|
||||
#define QOS_DEFAULT_AVERAGE_PACKET_RATE 0x3FFF
|
||||
#define QOS_DEFAULT_BURST_SIZE_IN_APR 0x3F
|
||||
#define QOS_DEFAULT_PEAK_PACKET_RATE 2
|
||||
#define QOS_DEFAULT_SCHEDULER_ABILITY_APR 1 /*disable*/
|
||||
#define QOS_DEFAULT_SCHEDULER_ABILITY_PPR 1 /*disable*/
|
||||
#define QOS_DEFAULT_SCHEDULER_ABILITY_WFQ 1 /*disable*/
|
||||
|
||||
#define QOS_WEIGHT_MAX 128
|
||||
|
||||
#define LED_GROUP_MAX 3
|
||||
|
||||
#define ACL_DEFAULT_ABILITY 0
|
||||
#define ACL_DEFAULT_UNMATCH_PERMIT 1
|
||||
|
||||
#define ACL_RULE_FREE 0
|
||||
#define ACL_RULE_INAVAILABLE 1
|
||||
|
||||
#define FILTER_POLICING_MAX 8
|
||||
#define FILTER_LOGGING_MAX 8
|
||||
#define FILTER_PATTERN_MAX 4
|
||||
|
||||
#define STORM_UNUC_INDEX 39
|
||||
#define STORM_UNMC_INDEX 47
|
||||
#define STORM_MC_INDEX 55
|
||||
#define STORM_BC_INDEX 63
|
||||
|
||||
#define RTK_MAX_NUM_OF_INTERRUPT_TYPE 1
|
||||
#define RTK_MAX_NUM_OF_LED_GROUP 3
|
||||
#define RTK_TOTAL_NUM_OF_WORD_FOR_1BIT_PORT_LIST 1
|
||||
#define RTK_MAX_NUM_OF_PRIORITY 8
|
||||
#define RTK_MAX_NUM_OF_QUEUE 8
|
||||
#define RTK_MAX_NUM_OF_TRUNK_HASH_VAL 1
|
||||
#define RTK_MAX_NUM_OF_INTERRUPT_TYPE 1
|
||||
#define RTK_MAX_NUM_OF_PORT 10
|
||||
#define RTK_PORT_ID_MAX (RTK_MAX_NUM_OF_PORT - 1)
|
||||
#define RTK_PHY_ID_MAX (RTK_MAX_NUM_OF_PORT - 3)
|
||||
#define RTK_QUEUE_ID_MAX (RTK_MAX_NUM_OF_QUEUE - 1)
|
||||
#define RTK_MAX_NUM_OF_PROTO_TYPE 0xFFFF
|
||||
#define RTK_MAX_NUM_OF_MSTI 16
|
||||
#define RTK_MAX_NUM_OF_LEARN_LIMIT 0x2040
|
||||
#define RTK_MAX_PORT_MASK 0x3FF
|
||||
#define RTK_MAX_INPUT_RATE (0x1FFFF * 8)
|
||||
#define RTK_MIN_INPUT_RATE 8
|
||||
#define RTK_RATE_GRANULARTY_UNIT 8
|
||||
#define RTK_DOT1X_PAE 3
|
||||
#define RTK_L2_DEFAULT_TIME 6
|
||||
#define RTK_L2_DEFAULT_SPEED 2
|
||||
#define RTK_MAX_NUM_OF_SVLAN_INDEX 64
|
||||
#define RTK_MAX_NUM_OF_SP2C_INDEX 128
|
||||
#define RTK_MAX_NUM_OF_MC2S_INDEX 32
|
||||
#define RTK_MAX_NUM_OF_C2S_INDEX 128
|
||||
#define RTK_VLAN_ID_MIN 0
|
||||
#define RTK_VLAN_ID_MAX 4095
|
||||
#define RTK_DOT1P_PRIORITY_MAX 7
|
||||
#define RTK_MAX_NUM_OF_FILTER_TYPE 5
|
||||
#define RTK_MAX_NUM_OF_FILTER_FIELD 7
|
||||
#define RTK_MAX_NUM_OF_FILTER_PORT 16
|
||||
#define RTK_MAX_NUM_OF_METER 64
|
||||
#define RTK_QOS_RATE_INPUT_MAX (0x1FFFF * 8)
|
||||
#define RTK_QOS_RATE_INPUT_MIN 8
|
||||
#define RTK_VALUE_OF_DSCP_MAX 63
|
||||
#define RTK_VALUE_OF_DSCP_MIN 0
|
||||
#define RTK_EFID_MAX 0x7
|
||||
#define RTK_FID_MAX 0xFFF
|
||||
#define RTK_MAX_NUM_OF_VLAN_INDEX 32
|
||||
#define RTK_MAX_NUM_OF_PROTOVLAN_GROUP 4
|
||||
#define RTK_PROTOVLAN_GROUP_ID_MAX (RTK_MAX_NUM_OF_PROTOVLAN_GROUP - 1)
|
||||
#define RTK_MAX_NUM_OF_ACL_RULE 64
|
||||
#define RTK_SVLAN_TPID 0x88a8
|
||||
#define RTK_PORT_TRUNK_GROUP_MASK(group) (0xF << (group << 2))
|
||||
#define RTK_PORT_TRUNK_GROUP_OFFSET(group) (group << 2)
|
||||
|
||||
#define RTK_INDRECT_ACCESS_CRTL 0x1f00
|
||||
#define RTK_INDRECT_ACCESS_STATUS 0x1f01
|
||||
#define RTK_INDRECT_ACCESS_ADDRESS 0x1f02
|
||||
#define RTK_INDRECT_ACCESS_WRITE_DATA 0x1f03
|
||||
#define RTK_INDRECT_ACCESS_READ_DATA 0x1f04
|
||||
#define RTK_INDRECT_ACCESS_DELAY 0x1f80
|
||||
#define RTK_INDRECT_ACCESS_BURST 0x1f81
|
||||
#define RTK_RW_MASK 0x2
|
||||
#define RTK_CMD_MASK 0x1
|
||||
#define RTK_PHY_BUSY_OFFSET 2
|
||||
|
||||
#define RTK_WHOLE_SYSTEM 0xFF
|
||||
|
||||
#define RTK_EXT_0 0
|
||||
#define RTK_EXT_1 1
|
||||
|
||||
#define RTK_EXT_0_MAC 9
|
||||
#define RTK_EXT_1_MAC 8
|
||||
|
||||
#ifndef MAC_ADDR_LEN
|
||||
#define MAC_ADDR_LEN 6
|
||||
#endif
|
||||
|
||||
#define IPV6_ADDR_LEN 16
|
||||
#define IPV4_ADDR_LEN 4
|
||||
|
||||
#define RTK_DOT_1AS_TIMESTAMP_UNIT_IN_WORD_LENGTH 3UL
|
||||
|
||||
#define RTK_IPV6_ADDR_WORD_LENGTH 4UL
|
||||
|
||||
typedef enum rtk_cpu_insert_e
|
||||
{
|
||||
CPU_INSERT_TO_ALL = 0,
|
||||
CPU_INSERT_TO_TRAPPING,
|
||||
CPU_INSERT_TO_NONE,
|
||||
CPU_INSERT_END
|
||||
} rtk_cpu_insert_t;
|
||||
|
||||
typedef enum rtk_cpu_position_e
|
||||
{
|
||||
CPU_POS_ATTER_DA = 0,
|
||||
CPU_POS_AFTER_CRC,
|
||||
CPU_POS_END
|
||||
} rtk_cpu_position_t;
|
||||
|
||||
typedef uint32 rtk_data_t;
|
||||
|
||||
/* Type of port-based dot1x auth/unauth*/
|
||||
typedef enum rtk_dot1x_auth_status_e
|
||||
{
|
||||
UNAUTH = 0,
|
||||
AUTH,
|
||||
AUTH_STATUS_END
|
||||
} rtk_dot1x_auth_status_t;
|
||||
|
||||
typedef enum rtk_dot1x_direction_e
|
||||
{
|
||||
BOTH = 0,
|
||||
IN,
|
||||
DIRECTION_END
|
||||
} rtk_dot1x_direction_t;
|
||||
|
||||
typedef enum rtk_mode_ext_e
|
||||
{
|
||||
MODE_EXT_DISABLE = 0,
|
||||
MODE_EXT_RGMII,
|
||||
MODE_EXT_MII_MAC,
|
||||
MODE_EXT_MII_PHY,
|
||||
MODE_EXT_TMII_MAC,
|
||||
MODE_EXT_TMII_PHY,
|
||||
MODE_EXT_GMII,
|
||||
MODE_EXT_RGMII_33V,
|
||||
MODE_EXT_END
|
||||
} rtk_mode_ext_t;
|
||||
|
||||
typedef enum rtk_led_group_e
|
||||
{
|
||||
LED_GROUP_0 = 0,
|
||||
LED_GROUP_1,
|
||||
LED_GROUP_2,
|
||||
LED_GROUP_END
|
||||
} rtk_led_group_t;
|
||||
|
||||
typedef struct rtk_port_mac_ability_s
|
||||
{
|
||||
uint32 forcemode;
|
||||
uint32 speed;
|
||||
uint32 duplex;
|
||||
uint32 link;
|
||||
uint32 nway;
|
||||
uint32 txpause;
|
||||
uint32 rxpause;
|
||||
uint32 lpi100;
|
||||
uint32 lpi1000;
|
||||
} rtk_port_mac_ability_t;
|
||||
|
||||
typedef struct rtk_portmask_s
|
||||
{
|
||||
uint32 bits[RTK_TOTAL_NUM_OF_WORD_FOR_1BIT_PORT_LIST];
|
||||
} rtk_portmask_t;
|
||||
|
||||
int RTL8370_init(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,344 @@
|
|||
/*
|
||||
* Copyright(c) Realtek Semiconductor Corporation, 2008
|
||||
* All rights reserved.
|
||||
*
|
||||
* $Revision$
|
||||
* $Date$
|
||||
*
|
||||
* Purpose : Definition the error number in the SDK.
|
||||
*
|
||||
* Feature : error definition
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __RTK_API_EXT_H__
|
||||
#define __RTK_API_EXT_H__
|
||||
|
||||
/*
|
||||
* Include Files
|
||||
*/
|
||||
#include <rtk_types.h>
|
||||
#include <rtk_api.h>
|
||||
|
||||
/*
|
||||
* Function Declaration
|
||||
*/
|
||||
/*Misc 3*/
|
||||
/*extern rtk_api_ret_t rtk_switch_init(void);
|
||||
extern rtk_api_ret_t rtk_switch_maxPktLen_set(rtk_switch_maxPktLen_t len);
|
||||
extern rtk_api_ret_t rtk_switch_maxPktLen_get(rtk_switch_maxPktLen_t *pLen);
|
||||
extern rtk_api_ret_t rtk_switch_greenEthernet_set(rtk_enable_t enable);
|
||||
extern rtk_api_ret_t rtk_switch_greenEthernet_get(rtk_data_t *pEnable);*/
|
||||
|
||||
/* Rate 5*/
|
||||
/*extern rtk_api_ret_t rtk_rate_shareMeter_set(rtk_meter_id_t index, rtk_rate_t rate, rtk_enable_t ifg_include);
|
||||
extern rtk_api_ret_t rtk_rate_shareMeter_get(rtk_meter_id_t index, rtk_rate_t *pRate ,rtk_enable_t *pIfg_include);
|
||||
extern rtk_api_ret_t rtk_rate_igrBandwidthCtrlRate_set( rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_include, rtk_enable_t fc_enable);
|
||||
extern rtk_api_ret_t rtk_rate_igrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include, rtk_enable_t *pFc_enable);
|
||||
extern rtk_api_ret_t rtk_rate_egrBandwidthCtrlRate_set(rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_includ);
|
||||
extern rtk_api_ret_t rtk_rate_egrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include);
|
||||
extern rtk_api_ret_t rtk_rate_egrQueueBwCtrlEnable_set(rtk_port_t port, rtk_qid_t queue, rtk_enable_t enable);
|
||||
extern rtk_api_ret_t rtk_rate_egrQueueBwCtrlEnable_get(rtk_port_t port, rtk_qid_t queue, rtk_enable_t *pEnable);
|
||||
extern rtk_api_ret_t rtk_rate_egrQueueBwCtrlRate_get(rtk_port_t port, rtk_qid_t queue, rtk_data_t *pIndex);
|
||||
extern rtk_api_ret_t rtk_rate_egrQueueBwCtrlRate_set(rtk_port_t port, rtk_qid_t queue, rtk_data_t index);*/
|
||||
|
||||
/*Storm Control Rate 2*/
|
||||
/*#if defined(EMBEDDED_SUPPORT)
|
||||
extern rtk_api_ret_t rtk_storm_controlRate_set(rtk_port_t port, rtk_rate_storm_group_t storm_type, rtk_rate_t rate, rtk_enable_t ifg_include, uint32 mode) reentrant;
|
||||
extern rtk_api_ret_t rtk_storm_controlRate_get(rtk_port_t port, rtk_rate_storm_group_t storm_type, rtk_rate_t *pRate, rtk_enable_t *pIfg_include, uint32 mode) reentrant;
|
||||
#else
|
||||
extern rtk_api_ret_t rtk_storm_controlRate_set(rtk_port_t port, rtk_rate_storm_group_t storm_type, rtk_rate_t rate, rtk_enable_t ifg_include, uint32 mode);
|
||||
extern rtk_api_ret_t rtk_storm_controlRate_get(rtk_port_t port, rtk_rate_storm_group_t storm_type, rtk_rate_t *pRate, rtk_enable_t *pIfg_include, uint32 mode);
|
||||
#endif
|
||||
extern rtk_api_ret_t rtk_storm_bypass_set(rtk_storm_bypass_t type, rtk_enable_t enable);
|
||||
extern rtk_api_ret_t rtk_storm_bypass_get(rtk_storm_bypass_t type, rtk_enable_t *pEnable);*/
|
||||
|
||||
/* QoS 12 */
|
||||
/*extern rtk_api_ret_t rtk_qos_init(rtk_queue_num_t queueNum);
|
||||
extern rtk_api_ret_t rtk_qos_priSel_set(rtk_priority_select_t *pPriDec);
|
||||
extern rtk_api_ret_t rtk_qos_priSel_get(rtk_priority_select_t *pPriDec);
|
||||
extern rtk_api_ret_t rtk_qos_1pPriRemap_set(rtk_pri_t dot1p_pri, rtk_pri_t int_pri);
|
||||
extern rtk_api_ret_t rtk_qos_1pPriRemap_get(rtk_pri_t dot1p_pri, rtk_pri_t *pInt_pri);
|
||||
extern rtk_api_ret_t rtk_qos_dscpPriRemap_set(rtk_dscp_t dscp, rtk_pri_t int_pri);
|
||||
extern rtk_api_ret_t rtk_qos_dscpPriRemap_get(rtk_dscp_t dscp, rtk_pri_t *pInt_pri);
|
||||
extern rtk_api_ret_t rtk_qos_portPri_set(rtk_port_t port, rtk_pri_t int_pri) ;
|
||||
extern rtk_api_ret_t rtk_qos_portPri_get(rtk_port_t port, rtk_pri_t *pInt_pri) ;
|
||||
extern rtk_api_ret_t rtk_qos_queueNum_set(rtk_port_t port, rtk_queue_num_t queue_num);
|
||||
extern rtk_api_ret_t rtk_qos_queueNum_get(rtk_port_t port, rtk_queue_num_t *pQueue_num);
|
||||
extern rtk_api_ret_t rtk_qos_priMap_set(rtk_queue_num_t queue_num, rtk_qos_pri2queue_t *pPri2qid);
|
||||
extern rtk_api_ret_t rtk_qos_priMap_get(rtk_queue_num_t queue_num, rtk_qos_pri2queue_t *pPri2qid);
|
||||
extern rtk_api_ret_t rtk_qos_schedulingQueue_set(rtk_port_t port, rtk_qos_queue_weights_t *pQweights);
|
||||
extern rtk_api_ret_t rtk_qos_schedulingQueue_get(rtk_port_t port, rtk_qos_queue_weights_t *pQweights);
|
||||
extern rtk_api_ret_t rtk_qos_schedulingAlgorithm_get(rtk_port_t port, rtk_qos_scheduling_type_t *pScheduling_type);
|
||||
extern rtk_api_ret_t rtk_qos_schedulingAlgorithm_set(rtk_port_t port, rtk_qos_scheduling_type_t scheduling_type);
|
||||
extern rtk_api_ret_t rtk_qos_1pRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable);
|
||||
extern rtk_api_ret_t rtk_qos_1pRemarkEnable_set(rtk_port_t port, rtk_enable_t enable);
|
||||
extern rtk_api_ret_t rtk_qos_1pRemark_set(rtk_pri_t int_pri, rtk_pri_t dot1p_pri);
|
||||
extern rtk_api_ret_t rtk_qos_1pRemark_get(rtk_pri_t int_pri, rtk_pri_t *pDot1p_pri);
|
||||
extern rtk_api_ret_t rtk_qos_dscpRemarkEnable_set(rtk_port_t port, rtk_enable_t enable);
|
||||
extern rtk_api_ret_t rtk_qos_dscpRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable);
|
||||
extern rtk_api_ret_t rtk_qos_dscpRemark_set(rtk_pri_t int_pri, rtk_dscp_t dscp);
|
||||
extern rtk_api_ret_t rtk_qos_dscpRemark_get(rtk_pri_t int_pri, rtk_dscp_t *pDscp);*/
|
||||
|
||||
/* Trap & Reserved Multicast Address (More Action like leaky, bypass storm not define) 5*/
|
||||
/*extern rtk_api_ret_t rtk_trap_unknownUnicastPktAction_set(rtk_trap_ucast_type_t type, rtk_trap_ucast_action_t ucast_action);
|
||||
extern rtk_api_ret_t rtk_trap_unknownUnicastPktAction_get(rtk_trap_ucast_type_t type, rtk_trap_ucast_action_t *pUcast_action);
|
||||
extern rtk_api_ret_t rtk_trap_unknownMcastPktAction_set(rtk_port_t port, rtk_mcast_type_t type, rtk_trap_mcast_action_t mcast_action);
|
||||
extern rtk_api_ret_t rtk_trap_unknownMcastPktAction_get(rtk_port_t port, rtk_mcast_type_t type, rtk_trap_mcast_action_t *pMcast_action);
|
||||
extern rtk_api_ret_t rtk_trap_igmpCtrlPktAction_set(rtk_igmp_type_t type, rtk_trap_igmp_action_t igmp_action);
|
||||
extern rtk_api_ret_t rtk_trap_igmpCtrlPktAction_get(rtk_igmp_type_t type, rtk_trap_igmp_action_t *pIgmp_action);
|
||||
extern rtk_api_ret_t rtk_trap_rmaAction_set(rtk_mac_t *pRma_frame, rtk_trap_rma_action_t rma_action);
|
||||
extern rtk_api_ret_t rtk_trap_rmaAction_get(rtk_mac_t *pRma_frame, rtk_trap_rma_action_t *pRma_action);
|
||||
extern rtk_api_ret_t rtk_trap_ethernetAv_set(rtk_enable_t enable);
|
||||
extern rtk_api_ret_t rtk_trap_ethernetAv_get(rtk_data_t *pEnable);*/
|
||||
|
||||
/* Leaky 2 */
|
||||
/*extern rtk_api_ret_t rtk_leaky_vlan_set(rtk_leaky_type_t type, rtk_enable_t enable);
|
||||
extern rtk_api_ret_t rtk_leaky_vlan_get(rtk_leaky_type_t type, rtk_enable_t *pEnable);
|
||||
extern rtk_api_ret_t rtk_leaky_portIsolation_set(rtk_leaky_type_t type, rtk_enable_t enable);
|
||||
extern rtk_api_ret_t rtk_leaky_portIsolation_get(rtk_leaky_type_t type, rtk_enable_t *pEnable);*/
|
||||
|
||||
/* Port and PHY setting 17 */
|
||||
/*extern rtk_api_ret_t rtk_port_phyAutoNegoAbility_set(rtk_port_t port, rtk_port_phy_ability_t *pAbility);
|
||||
extern rtk_api_ret_t rtk_port_phyAutoNegoAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility);
|
||||
extern rtk_api_ret_t rtk_port_phyForceModeAbility_set(rtk_port_t port, rtk_port_phy_ability_t *pAbility);
|
||||
extern rtk_api_ret_t rtk_port_phyForceModeAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility);
|
||||
extern rtk_api_ret_t rtk_port_phyStatus_get(rtk_port_t port, rtk_port_linkStatus_t *pLinkStatus, rtk_data_t *pSpeed, rtk_data_t *pDuplex);
|
||||
extern rtk_api_ret_t rtk_port_phyTestMode_set(rtk_port_t port, rtk_port_phy_test_mode_t mode);
|
||||
extern rtk_api_ret_t rtk_port_phyTestMode_get(rtk_port_t port, rtk_port_phy_test_mode_t *pMode);
|
||||
extern rtk_api_ret_t rtk_port_phy1000BaseTMasterSlave_set(rtk_port_t port, rtk_enable_t enabled, rtk_enable_t masterslave);
|
||||
extern rtk_api_ret_t rtk_port_macForceLink_set(rtk_port_t port, rtk_port_mac_ability_t *pPortability);
|
||||
extern rtk_api_ret_t rtk_port_macForceLink_get(rtk_port_t port, rtk_port_mac_ability_t *pPortability);
|
||||
extern rtk_api_ret_t rtk_port_macForceLinkExt0_set(rtk_mode_ext_t mode, rtk_port_mac_ability_t *pPortability);
|
||||
extern rtk_api_ret_t rtk_port_macForceLinkExt0_get(rtk_mode_ext_t *pMode, rtk_port_mac_ability_t *pPortability);
|
||||
extern rtk_api_ret_t rtk_port_macForceLinkExt1_set(rtk_mode_ext_t mode, rtk_port_mac_ability_t *pPortability);
|
||||
extern rtk_api_ret_t rtk_port_macForceLinkExt1_get(rtk_mode_ext_t *pMode, rtk_port_mac_ability_t *pPortability);
|
||||
extern rtk_api_ret_t rtk_port_macStatus_get(rtk_port_t port, rtk_port_mac_ability_t *pPortstatus);
|
||||
extern rtk_api_ret_t rtk_port_phyReg_set(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_port_phy_data_t value);
|
||||
extern rtk_api_ret_t rtk_port_phyReg_get(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_port_phy_data_t *pData);
|
||||
extern rtk_api_ret_t rtk_port_backpressureEnable_get(rtk_port_t port, rtk_enable_t *pEnable);
|
||||
extern rtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable_t enable);
|
||||
extern rtk_api_ret_t rtk_port_adminEnable_set(rtk_port_t port, rtk_enable_t enable);
|
||||
extern rtk_api_ret_t rtk_port_adminEnable_get(rtk_port_t port, rtk_enable_t *pEnable);
|
||||
extern rtk_api_ret_t rtk_port_isolation_set(rtk_port_t port, rtk_portmask_t portmask);
|
||||
extern rtk_api_ret_t rtk_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPortmask);
|
||||
extern rtk_api_ret_t rtk_port_rgmiiDelayExt0_set(rtk_data_t txDelay, rtk_data_t rxDelay);
|
||||
extern rtk_api_ret_t rtk_port_rgmiiDelayExt0_get(rtk_data_t *pTxDelay, rtk_data_t *pRxDelay);
|
||||
extern rtk_api_ret_t rtk_port_rgmiiDelayExt1_set(rtk_data_t txDelay, rtk_data_t rxDelay);
|
||||
extern rtk_api_ret_t rtk_port_rgmiiDelayExt1_get(rtk_data_t *pTxDelay, rtk_data_t *pRxDelay);
|
||||
extern rtk_api_ret_t rtk_port_phyEnableAll_set(rtk_enable_t enable);
|
||||
extern rtk_api_ret_t rtk_port_phyEnableAll_get(rtk_data_t *pEnable);
|
||||
extern rtk_api_ret_t rtk_port_efid_set(rtk_port_t port, rtk_data_t efid);
|
||||
extern rtk_api_ret_t rtk_port_efid_get(rtk_port_t port, rtk_data_t *pEfid);*/
|
||||
|
||||
/* CVLAN 10 */
|
||||
/*extern rtk_api_ret_t rtk_vlan_init(void);
|
||||
extern rtk_api_ret_t rtk_vlan_set(rtk_vlan_t vid, rtk_portmask_t mbrmsk, rtk_portmask_t untagmsk, rtk_fid_t fid);
|
||||
extern rtk_api_ret_t rtk_vlan_get(rtk_vlan_t vid, rtk_portmask_t *pMbrmsk, rtk_portmask_t *pUntagmsk, rtk_fid_t *pFid);
|
||||
extern rtk_api_ret_t rtk_vlan_portPvid_set(rtk_port_t port, rtk_vlan_t pvid, rtk_pri_t priority);
|
||||
extern rtk_api_ret_t rtk_vlan_portPvid_get(rtk_port_t port, rtk_vlan_t *pPvid, rtk_pri_t *pPriority);
|
||||
extern rtk_api_ret_t rtk_vlan_portIgrFilterEnable_set(rtk_port_t port, rtk_enable_t igr_filter);
|
||||
extern rtk_api_ret_t rtk_vlan_portIgrFilterEnable_get(rtk_port_t port, rtk_enable_t *pIgr_filter);
|
||||
extern rtk_api_ret_t rtk_vlan_portAcceptFrameType_set(rtk_port_t port, rtk_vlan_acceptFrameType_t accept_frame_type);
|
||||
extern rtk_api_ret_t rtk_vlan_portAcceptFrameType_get(rtk_port_t port, rtk_vlan_acceptFrameType_t *pAccept_frame_type);
|
||||
extern rtk_api_ret_t rtk_vlan_vlanBasedPriority_set(rtk_vlan_t vid, rtk_pri_t priority);
|
||||
extern rtk_api_ret_t rtk_vlan_vlanBasedPriority_get(rtk_vlan_t vid, rtk_pri_t *pPriority);
|
||||
extern rtk_api_ret_t rtk_vlan_tagMode_set(rtk_port_t port, rtk_vlan_tagMode_t tag_mode);
|
||||
extern rtk_api_ret_t rtk_vlan_tagMode_get(rtk_port_t port, rtk_vlan_tagMode_t *pTag_mode);
|
||||
extern rtk_api_ret_t rtk_vlan_stg_get(rtk_vlan_t vid, rtk_stg_t *pStg);
|
||||
extern rtk_api_ret_t rtk_vlan_stg_set(rtk_vlan_t vid, rtk_stg_t stg);
|
||||
extern rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_add(rtk_port_t port, rtk_vlan_protoAndPortInfo_t info);
|
||||
extern rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_get(rtk_port_t port, rtk_vlan_proto_type_t proto_type, rtk_vlan_protoVlan_frameType_t frame_type, rtk_vlan_protoAndPortInfo_t *pInfo);
|
||||
extern rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_del(rtk_port_t port, rtk_vlan_proto_type_t proto_type, rtk_vlan_protoVlan_frameType_t frame_type);
|
||||
extern rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_delAll(rtk_port_t port);
|
||||
extern rtk_api_ret_t rtk_vlan_portFid_set(rtk_port_t port, rtk_enable_t enable, rtk_fid_t fid);
|
||||
extern rtk_api_ret_t rtk_vlan_portFid_get(rtk_port_t port, rtk_data_t *pEnable, rtk_data_t *pFid);*/
|
||||
|
||||
/*Spanning Tree 2 */
|
||||
/*extern rtk_api_ret_t rtk_stp_init(void);
|
||||
extern rtk_api_ret_t rtk_stp_mstpState_set(rtk_stp_msti_id_t msti, rtk_port_t port, rtk_stp_state_t stp_state);
|
||||
extern rtk_api_ret_t rtk_stp_mstpState_get(rtk_stp_msti_id_t msti, rtk_port_t port, rtk_stp_state_t *pStp_state);*/
|
||||
|
||||
/* LUT 16 */
|
||||
/*extern rtk_api_ret_t rtk_l2_init(void);
|
||||
extern rtk_api_ret_t rtk_l2_addr_add(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data);
|
||||
extern rtk_api_ret_t rtk_l2_addr_get(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data);
|
||||
extern rtk_api_ret_t rtk_l2_addr_del(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data);
|
||||
extern rtk_api_ret_t rtk_l2_mcastAddr_add(rtk_mac_t *pMac, rtk_fid_t fid, rtk_portmask_t portmask);
|
||||
extern rtk_api_ret_t rtk_l2_mcastAddr_get(rtk_mac_t *pMac, rtk_fid_t fid, rtk_portmask_t *pPortmask);
|
||||
extern rtk_api_ret_t rtk_l2_mcastAddr_del(rtk_mac_t *pMac, rtk_fid_t fid);
|
||||
extern rtk_api_ret_t rtk_l2_ipMcastAddr_add(ipaddr_t sip, ipaddr_t dip, rtk_portmask_t portmask);
|
||||
extern rtk_api_ret_t rtk_l2_ipMcastAddr_get(ipaddr_t sip, ipaddr_t dip, rtk_portmask_t *pPortmask);
|
||||
extern rtk_api_ret_t rtk_l2_ipMcastAddr_del(ipaddr_t sip, ipaddr_t dip);
|
||||
extern rtk_api_ret_t rtk_l2_flushType_set(rtk_l2_flushType_t type, rtk_vlan_t vid, uint32 portOrTid);
|
||||
extern rtk_api_ret_t rtk_l2_flushLinkDownPortAddrEnable_get(rtk_port_t port, rtk_enable_t *pEnable);
|
||||
extern rtk_api_ret_t rtk_l2_flushLinkDownPortAddrEnable_set(rtk_port_t port, rtk_enable_t enable);
|
||||
extern rtk_api_ret_t rtk_l2_agingEnable_set(rtk_port_t port, rtk_enable_t enable);
|
||||
extern rtk_api_ret_t rtk_l2_agingEnable_get(rtk_port_t port, rtk_enable_t *pEnable);
|
||||
extern rtk_api_ret_t rtk_l2_limitLearningCnt_set(rtk_port_t port, rtk_mac_cnt_t mac_cnt);
|
||||
extern rtk_api_ret_t rtk_l2_limitLearningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt);
|
||||
extern rtk_api_ret_t rtk_l2_limitLearningCntAction_set(rtk_port_t port, rtk_l2_limitLearnCntAction_t action);
|
||||
extern rtk_api_ret_t rtk_l2_limitLearningCntAction_get(rtk_port_t port, rtk_l2_limitLearnCntAction_t *pAction);
|
||||
extern rtk_api_ret_t rtk_l2_learningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt);
|
||||
extern rtk_api_ret_t rtk_l2_floodPortMask_set(rtk_l2_flood_type_t floood_type, rtk_portmask_t flood_portmask);
|
||||
extern rtk_api_ret_t rtk_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, rtk_portmask_t *pFlood_portmask);
|
||||
extern rtk_api_ret_t rtk_l2_localPktPermit_set(rtk_port_t port, rtk_enable_t permit);
|
||||
extern rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit);
|
||||
extern rtk_api_ret_t rtk_l2_aging_get(rtk_l2_age_time_t *pAging_time);
|
||||
extern rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time);
|
||||
extern rtk_api_ret_t rtk_l2_hashMethod_set(rtk_hash_method_t mode);
|
||||
extern rtk_api_ret_t rtk_l2_hashMethod_get(rtk_hash_method_t *pMode);
|
||||
extern rtk_api_ret_t rtk_l2_ipMcastAddrLookup_set(rtk_l2_lookup_type_t type);
|
||||
extern rtk_api_ret_t rtk_l2_ipMcastAddrLookup_get(rtk_l2_lookup_type_t *pType);
|
||||
extern rtk_api_ret_t rtk_l2_entry_get(rtk_l2_addr_table_t *pL2_entry);*/
|
||||
|
||||
/* SVLAN 10 */
|
||||
/*extern rtk_api_ret_t rtk_svlan_init(void);
|
||||
extern rtk_api_ret_t rtk_svlan_servicePort_add(rtk_port_t port);
|
||||
extern rtk_api_ret_t rtk_svlan_servicePort_get(rtk_portmask_t *pSvlan_portmask);
|
||||
extern rtk_api_ret_t rtk_svlan_servicePort_del(rtk_port_t port);
|
||||
extern rtk_api_ret_t rtk_svlan_tpidEntry_set(uint32 svlan_tag_id);
|
||||
extern rtk_api_ret_t rtk_svlan_tpidEntry_get(uint32 *pSvlan_tag_id);
|
||||
extern rtk_api_ret_t rtk_svlan_priorityRef_set(rtk_svlan_pri_ref_t ref);
|
||||
extern rtk_api_ret_t rtk_svlan_priorityRef_get(rtk_svlan_pri_ref_t *pRef);
|
||||
extern rtk_api_ret_t rtk_svlan_memberPortEntry_set(uint32 svid_idx, rtk_svlan_memberCfg_t *psvlan_cfg);
|
||||
extern rtk_api_ret_t rtk_svlan_memberPortEntry_get(uint32 svid_idx, rtk_svlan_memberCfg_t *pSvlan_cfg);
|
||||
extern rtk_api_ret_t rtk_svlan_defaultSvlan_set(rtk_vlan_t svid);
|
||||
extern rtk_api_ret_t rtk_svlan_defaultSvlan_get(rtk_vlan_t *pSvid);
|
||||
extern rtk_api_ret_t rtk_svlan_c2s_add(rtk_vlan_t vid, rtk_port_t port, rtk_vlan_t svid);
|
||||
extern rtk_api_ret_t rtk_svlan_c2s_del(rtk_vlan_t vid, rtk_port_t port);
|
||||
extern rtk_api_ret_t rtk_svlan_c2s_get(rtk_vlan_t vid, rtk_port_t port, rtk_vlan_t *pSvid);
|
||||
extern rtk_api_ret_t rtk_svlan_ipmc2s_add(ipaddr_t ipmc, rtk_vlan_t svid);
|
||||
extern rtk_api_ret_t rtk_svlan_ipmc2s_del(ipaddr_t ipmc);
|
||||
extern rtk_api_ret_t rtk_svlan_ipmc2s_get(ipaddr_t ipmc, rtk_vlan_t *pSvid);
|
||||
extern rtk_api_ret_t rtk_svlan_l2mc2s_add(rtk_vlan_t svid, rtk_mac_t mac);
|
||||
extern rtk_api_ret_t rtk_svlan_l2mc2s_del(rtk_mac_t mac);
|
||||
extern rtk_api_ret_t rtk_svlan_l2mc2s_get(rtk_mac_t mac, rtk_vlan_t *pSvid);
|
||||
extern rtk_api_ret_t rtk_svlan_sp2c_add(rtk_vlan_t svid, rtk_port_t dst_port, rtk_vlan_t cvid);
|
||||
extern rtk_api_ret_t rtk_svlan_sp2c_get(rtk_vlan_t svid, rtk_port_t dst_port, rtk_vlan_t *pCvid);
|
||||
extern rtk_api_ret_t rtk_svlan_sp2c_del(rtk_vlan_t svid, rtk_port_t dst_port);*/
|
||||
|
||||
/* CPU Port 2 */
|
||||
/*extern rtk_api_ret_t rtk_cpu_enable_set(rtk_enable_t enable);
|
||||
extern rtk_api_ret_t rtk_cpu_enable_get(rtk_enable_t *pEnable);
|
||||
extern rtk_api_ret_t rtk_cpu_tagPort_set(rtk_port_t port, rtk_cpu_insert_t mode);
|
||||
extern rtk_api_ret_t rtk_cpu_tagPort_get(rtk_port_t *pPort, rtk_cpu_insert_t *pMode);*/
|
||||
|
||||
/* 802.1X 10 */
|
||||
/*extern rtk_api_ret_t rtk_dot1x_unauthPacketOper_get(rtk_port_t port, rtk_dot1x_unauth_action_t *pUnauth_action);
|
||||
extern rtk_api_ret_t rtk_dot1x_unauthPacketOper_set(rtk_port_t port, rtk_dot1x_unauth_action_t unauth_action);
|
||||
extern rtk_api_ret_t rtk_dot1x_eapolFrame2CpuEnable_get(rtk_enable_t *pEnable);
|
||||
extern rtk_api_ret_t rtk_dot1x_eapolFrame2CpuEnable_set(rtk_enable_t enable);
|
||||
extern rtk_api_ret_t rtk_dot1x_portBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable);
|
||||
extern rtk_api_ret_t rtk_dot1x_portBasedEnable_set(rtk_port_t port, rtk_enable_t enable);
|
||||
extern rtk_api_ret_t rtk_dot1x_portBasedAuthStatus_get(rtk_port_t port, rtk_dot1x_auth_status_t *pPort_auth);
|
||||
extern rtk_api_ret_t rtk_dot1x_portBasedAuthStatus_set(rtk_port_t port, rtk_dot1x_auth_status_t port_auth);
|
||||
extern rtk_api_ret_t rtk_dot1x_portBasedDirection_get(rtk_port_t port, rtk_dot1x_direction_t *pPort_direction);
|
||||
extern rtk_api_ret_t rtk_dot1x_portBasedDirection_set(rtk_port_t port, rtk_dot1x_direction_t port_direction);
|
||||
extern rtk_api_ret_t rtk_dot1x_macBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable);
|
||||
extern rtk_api_ret_t rtk_dot1x_macBasedEnable_set(rtk_port_t port, rtk_enable_t enable);
|
||||
extern rtk_api_ret_t rtk_dot1x_macBasedAuthMac_add(rtk_port_t port, rtk_mac_t *pAuth_mac, rtk_fid_t fid);
|
||||
extern rtk_api_ret_t rtk_dot1x_macBasedAuthMac_del(rtk_port_t port, rtk_mac_t *pAuth_mac, rtk_fid_t fid);
|
||||
extern rtk_api_ret_t rtk_dot1x_macBasedDirection_get(rtk_dot1x_direction_t *pMac_direction);
|
||||
extern rtk_api_ret_t rtk_dot1x_macBasedDirection_set(rtk_dot1x_direction_t mac_direction);
|
||||
extern rtk_api_ret_t rtk_dot1x_guestVlan_set(rtk_vlan_t vid);
|
||||
extern rtk_api_ret_t rtk_dot1x_guestVlan_get(rtk_vlan_t *pVid);
|
||||
extern rtk_api_ret_t rtk_dot1x_guestVlan2Auth_set(rtk_enable_t enable);
|
||||
extern rtk_api_ret_t rtk_dot1x_guestVlan2Auth_get(rtk_enable_t *pEnable);*/
|
||||
|
||||
/* Port Trunk 3 */
|
||||
/*extern rtk_api_ret_t rtk_trunk_port_get(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask);
|
||||
extern rtk_api_ret_t rtk_trunk_port_set(rtk_trunk_group_t trk_gid, rtk_portmask_t trunk_member_portmask);
|
||||
extern rtk_api_ret_t rtk_trunk_distributionAlgorithm_get(rtk_trunk_group_t trk_gid, rtk_trunk_hashVal2Port_t *pAlgo_bitmask);
|
||||
extern rtk_api_ret_t rtk_trunk_distributionAlgorithm_set(rtk_trunk_group_t trk_gid, rtk_trunk_hashVal2Port_t algo_bitmask);
|
||||
extern rtk_api_ret_t rtk_trunk_qeueuEmptyStatus_get(rtk_portmask_t *pPortmask);*/
|
||||
|
||||
/*Port Mirror 2 */
|
||||
/*extern rtk_api_ret_t rtk_mirror_portBased_set(rtk_port_t mirroring_port, rtk_portmask_t *pMirrored_rx_portmask, rtk_portmask_t *pMirrored_tx_portmask);
|
||||
extern rtk_api_ret_t rtk_mirror_portBased_get(rtk_port_t* pMirroring_port, rtk_portmask_t *pMirrored_rx_portmask, rtk_portmask_t *pMirrored_tx_portmask);
|
||||
extern rtk_api_ret_t rtk_mirror_portIso_set(rtk_enable_t enable);
|
||||
extern rtk_api_ret_t rtk_mirror_portIso_get(rtk_enable_t *pEnable);*/
|
||||
|
||||
/* MIB 4 */
|
||||
/*#ifdef EMBEDDED_SUPPORT
|
||||
extern rtk_api_ret_t rtk_stat_global_reset(void);
|
||||
extern rtk_api_ret_t rtk_stat_port_reset(rtk_port_t port);
|
||||
extern rtk_api_ret_t rtk_stat_port_get(rtk_port_t port, rtk_stat_port_type_t cntr_idx, rtk_stat_counter_t *pCntrH, rtk_stat_counter_t *pCntrL);
|
||||
extern rtk_api_ret_t rtk_stat_global_get(rtk_stat_global_type_t cntr_idx, rtk_stat_counter_t *pCntrH, rtk_stat_counter_t *pCntrL);
|
||||
#else
|
||||
extern rtk_api_ret_t rtk_stat_global_reset(void);
|
||||
extern rtk_api_ret_t rtk_stat_port_reset(rtk_port_t port);
|
||||
extern rtk_api_ret_t rtk_stat_global_get(rtk_stat_global_type_t cntr_idx, rtk_stat_counter_t *pCntr);
|
||||
extern rtk_api_ret_t rtk_stat_global_getAll(rtk_stat_global_cntr_t *pGlobal_cntrs);
|
||||
extern rtk_api_ret_t rtk_stat_port_get(rtk_port_t port, rtk_stat_port_type_t cntr_idx, rtk_stat_counter_t *pCntr);
|
||||
extern rtk_api_ret_t rtk_stat_port_getAll(rtk_port_t port, rtk_stat_port_cntr_t *pPort_cntrs);
|
||||
#endif*/
|
||||
|
||||
/* Interrupt 4 */
|
||||
/*extern rtk_api_ret_t rtk_int_polarity_set(rtk_int_polarity_t type);
|
||||
extern rtk_api_ret_t rtk_int_polarity_get(rtk_int_polarity_t *pType);
|
||||
extern rtk_api_ret_t rtk_int_control_set(rtk_int_type_t type, rtk_enable_t enable);
|
||||
extern rtk_api_ret_t rtk_int_control_get(rtk_int_type_t type, rtk_enable_t* pEnable);
|
||||
extern rtk_api_ret_t rtk_int_status_set(rtk_int_status_t statusMask);
|
||||
extern rtk_api_ret_t rtk_int_status_get(rtk_int_status_t* pStatusMask);
|
||||
extern rtk_api_ret_t rtk_int_advanceInfo_get(rtk_int_advType_t adv_type, rtk_int_info_t* info);*/
|
||||
|
||||
/*LED 7 */
|
||||
/*extern rtk_api_ret_t rtk_led_enable_set(rtk_led_group_t group, rtk_portmask_t portmask);
|
||||
extern rtk_api_ret_t rtk_led_enable_get(rtk_led_group_t group, rtk_portmask_t *pPortmask);
|
||||
extern rtk_api_ret_t rtk_led_operation_set(rtk_led_operation_t mode);
|
||||
extern rtk_api_ret_t rtk_led_operation_get(rtk_data_t *pMode);
|
||||
extern rtk_api_ret_t rtk_led_mode_set(rtk_led_mode_t mode);
|
||||
extern rtk_api_ret_t rtk_led_mode_get(rtk_led_mode_t *pMode);
|
||||
extern rtk_api_ret_t rtk_led_modeForce_set(rtk_led_group_t group, rtk_led_force_mode_t mode);
|
||||
extern rtk_api_ret_t rtk_led_modeForce_get(rtk_led_group_t group, rtk_data_t *pMode);
|
||||
extern rtk_api_ret_t rtk_led_blinkRate_set(rtk_led_blink_rate_t blinkRate);
|
||||
extern rtk_api_ret_t rtk_led_blinkRate_get(rtk_led_blink_rate_t *pBlinkRate);
|
||||
extern rtk_api_ret_t rtk_led_groupConfig_set(rtk_led_group_t group, rtk_led_congig_t config);
|
||||
extern rtk_api_ret_t rtk_led_groupConfig_get(rtk_led_group_t group, rtk_data_t *pConfig);
|
||||
extern rtk_api_ret_t rtk_led_serialMode_set(rtk_led_active_t active);
|
||||
extern rtk_api_ret_t rtk_led_serialMode_get(rtk_data_t *pActive);*/
|
||||
|
||||
/*Green ethernet 1 */
|
||||
/*extern rtk_api_ret_t rtk_green_feature_set(uint32 greenFeature, uint32 powerSaving);
|
||||
extern rtk_api_ret_t rtk_green_feature_get(uint32 greenFeature, uint32 powerSaving);*/
|
||||
|
||||
/*ACL APIs 7 */
|
||||
/*extern rtk_api_ret_t rtk_filter_igrAcl_init(void);
|
||||
extern rtk_api_ret_t rtk_filter_igrAcl_field_add(rtk_filter_cfg_t *pFilter_cfg, rtk_filter_field_t *pFilter_field);
|
||||
extern rtk_api_ret_t rtk_filter_igrAcl_cfg_add(rtk_filter_id_t filter_id, rtk_filter_cfg_t *pFilter_cfg, rtk_filter_action_t *pAction, rtk_filter_number_t *ruleNum);
|
||||
extern rtk_api_ret_t rtk_filter_igrAcl_cfg_del(rtk_filter_id_t filter_id);
|
||||
extern rtk_api_ret_t rtk_filter_igrAcl_cfg_delAll(void);
|
||||
extern rtk_api_ret_t rtk_filter_igrAcl_cfg_set(rtk_filter_id_t filter_id, rtk_filter_template_index_t template_index, rtk_filter_cfg_raw_t *pFilter_cfg, rtk_filter_action_t *pFilter_action);
|
||||
extern rtk_api_ret_t rtk_filter_igrAcl_cfg_get(rtk_filter_id_t filter_id, rtk_filter_cfg_raw_t *pFilter_cfg, rtk_filter_action_t *pAction);
|
||||
extern rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_set(rtk_port_t port, rtk_filter_unmatch_action_t action);
|
||||
extern rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_get(rtk_port_t port, rtk_filter_unmatch_action_t* action);
|
||||
extern rtk_api_ret_t rtk_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t state);
|
||||
extern rtk_api_ret_t rtk_filter_igrAcl_state_get(rtk_port_t port, rtk_filter_state_t* state);
|
||||
extern rtk_api_ret_t rtk_filter_igrAcl_template_set(rtk_filter_template_t *aclTemplate);
|
||||
extern rtk_api_ret_t rtk_filter_igrAcl_template_get(rtk_filter_template_t *aclTemplate);*/
|
||||
|
||||
/*RLDP APIs 3 */
|
||||
/*extern rtk_api_ret_t rtk_rldp_init(rtk_portmask_t txPortmask, rtk_mac_t Mac);
|
||||
extern rtk_api_ret_t rtk_rldp_getLoopPortmask(rtk_portmask_t* loopedPortmask);
|
||||
extern rtk_api_ret_t rtk_rldp_getLoopedPortPair(uint32 port, uint32 *portPair);*/
|
||||
|
||||
/*EEE APIs 2*/
|
||||
/*extern rtk_api_ret_t rtk_eee_init(void);
|
||||
extern rtk_api_ret_t rtk_eee_portEnable_set(rtk_port_t port, rtk_enable_t enable);
|
||||
extern rtk_api_ret_t rtk_eee_portEnable_get(rtk_port_t port, rtk_data_t *pEnable);
|
||||
|
||||
extern rtk_api_ret_t rtk_8307_init(void);
|
||||
extern rtk_api_ret_t rtk_patch_set(void);
|
||||
extern rtk_api_ret_t rtk_aldp_init(void);
|
||||
extern rtk_api_ret_t rtk_aldp_enable_set(rtk_enable_t enable);
|
||||
extern rtk_api_ret_t rtk_aldp_enable_get(rtk_data_t *pEnable);
|
||||
|
||||
extern rtk_api_ret_t rtk_port_phyTestModeAlpha_set(rtk_port_t port, rtk_port_phy_test_mode_t mode);
|
||||
|
||||
|
||||
extern rtk_api_ret_t rtk_port_rtct_init(void);
|
||||
extern rtk_api_ret_t rtk_port_rtctEnable_set(rtk_portmask_t portmask);
|
||||
extern rtk_api_ret_t rtk_port_rtctResult_get(rtk_port_t port, rtk_rtctResult_t *pRtctResult);*/
|
||||
|
||||
#endif /* __RTK_API_EXT_H__ */
|
||||
|
|
@ -0,0 +1,221 @@
|
|||
/*
|
||||
* Copyright(c) Realtek Semiconductor Corporation, 2008
|
||||
* All rights reserved.
|
||||
*
|
||||
* $Revision$
|
||||
* $Date$
|
||||
*
|
||||
* Purpose : Definition the error number in the SDK.
|
||||
*
|
||||
* Feature : error definition
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __COMMON_RT_ERROR_H__
|
||||
#define __COMMON_RT_ERROR_H__
|
||||
|
||||
/*
|
||||
* Include Files
|
||||
*/
|
||||
|
||||
/*
|
||||
* Data Type Declaration
|
||||
*/
|
||||
typedef enum rt_error_code_e
|
||||
{
|
||||
RT_ERR_FAILED = -1, /* General Error */
|
||||
|
||||
/* 0x0000xxxx for common error code */
|
||||
RT_ERR_OK = 0, /* 0x00000000, OK */
|
||||
RT_ERR_INPUT, /* 0x00000001, invalid input parameter */
|
||||
RT_ERR_UNIT_ID, /* 0x00000002, invalid unit id */
|
||||
RT_ERR_PORT_ID, /* 0x00000003, invalid port id */
|
||||
RT_ERR_PORT_MASK, /* 0x00000004, invalid port mask */
|
||||
RT_ERR_PORT_LINKDOWN, /* 0x00000005, link down port status */
|
||||
RT_ERR_ENTRY_INDEX, /* 0x00000006, invalid entry index */
|
||||
RT_ERR_NULL_POINTER, /* 0x00000007, input parameter is null pointer */
|
||||
RT_ERR_QUEUE_ID, /* 0x00000008, invalid queue id */
|
||||
RT_ERR_QUEUE_NUM, /* 0x00000009, invalid queue number */
|
||||
RT_ERR_BUSYWAIT_TIMEOUT, /* 0x0000000a, busy watting time out */
|
||||
RT_ERR_MAC, /* 0x0000000b, invalid mac address */
|
||||
RT_ERR_OUT_OF_RANGE, /* 0x0000000c, input parameter out of range */
|
||||
RT_ERR_CHIP_NOT_SUPPORTED, /* 0x0000000d, functions not supported by this chip model */
|
||||
RT_ERR_SMI, /* 0x0000000e, SMI error */
|
||||
RT_ERR_NOT_INIT, /* 0x0000000f, The module is not initial */
|
||||
RT_ERR_CHIP_NOT_FOUND, /* 0x00000010, The chip can not found */
|
||||
RT_ERR_NOT_ALLOWED, /* 0x00000011, actions not allowed by the function */
|
||||
RT_ERR_DRIVER_NOT_FOUND, /* 0x00000012, The driver can not found */
|
||||
RT_ERR_SEM_LOCK_FAILED, /* 0x00000013, Failed to lock semaphore */
|
||||
RT_ERR_SEM_UNLOCK_FAILED, /* 0x00000014, Failed to unlock semaphore */
|
||||
RT_ERR_ENABLE, /* 0x00000015, invalid enable parameter */
|
||||
RT_ERR_TBL_FULL, /* 0x00000016, input table full */
|
||||
|
||||
/* 0x0001xxxx for vlan */
|
||||
RT_ERR_VLAN_VID = 0x00010000, /* 0x00010000, invalid vid */
|
||||
RT_ERR_VLAN_PRIORITY, /* 0x00010001, invalid 1p priority */
|
||||
RT_ERR_VLAN_EMPTY_ENTRY, /* 0x00010002, emtpy entry of vlan table */
|
||||
RT_ERR_VLAN_ACCEPT_FRAME_TYPE, /* 0x00010003, invalid accept frame type */
|
||||
RT_ERR_VLAN_EXIST, /* 0x00010004, vlan is exist */
|
||||
RT_ERR_VLAN_ENTRY_NOT_FOUND, /* 0x00010005, specified vlan entry not found */
|
||||
RT_ERR_VLAN_PORT_MBR_EXIST, /* 0x00010006, member port exist in the specified vlan */
|
||||
RT_ERR_VLAN_PROTO_AND_PORT, /* 0x00010008, invalid protocol and port based vlan */
|
||||
|
||||
/* 0x0002xxxx for svlan */
|
||||
RT_ERR_SVLAN_ENTRY_INDEX = 0x00020000, /* 0x00020000, invalid svid entry no */
|
||||
RT_ERR_SVLAN_ETHER_TYPE, /* 0x00020001, invalid SVLAN ether type */
|
||||
RT_ERR_SVLAN_TABLE_FULL, /* 0x00020002, no empty entry in SVLAN table */
|
||||
RT_ERR_SVLAN_ENTRY_NOT_FOUND, /* 0x00020003, specified svlan entry not found */
|
||||
RT_ERR_SVLAN_EXIST, /* 0x00020004, SVLAN entry is exist */
|
||||
RT_ERR_SVLAN_VID, /* 0x00020005, invalid svid */
|
||||
|
||||
/* 0x0003xxxx for MSTP */
|
||||
RT_ERR_MSTI = 0x00030000, /* 0x00030000, invalid msti */
|
||||
RT_ERR_MSTP_STATE, /* 0x00030001, invalid spanning tree status */
|
||||
RT_ERR_MSTI_EXIST, /* 0x00030002, MSTI exist */
|
||||
RT_ERR_MSTI_NOT_EXIST, /* 0x00030003, MSTI not exist */
|
||||
|
||||
/* 0x0004xxxx for BUCKET */
|
||||
RT_ERR_TIMESLOT = 0x00040000, /* 0x00040000, invalid time slot */
|
||||
RT_ERR_TOKEN, /* 0x00040001, invalid token amount */
|
||||
RT_ERR_RATE, /* 0x00040002, invalid rate */
|
||||
RT_ERR_TICK, /* 0x00040003, invalid tick */
|
||||
|
||||
/* 0x0005xxxx for RMA */
|
||||
RT_ERR_RMA_ADDR = 0x00050000, /* 0x00050000, invalid rma mac address */
|
||||
RT_ERR_RMA_ACTION, /* 0x00050001, invalid rma action */
|
||||
|
||||
/* 0x0006xxxx for L2 */
|
||||
RT_ERR_L2_HASH_KEY = 0x00060000, /* 0x00060000, invalid L2 Hash key */
|
||||
RT_ERR_L2_HASH_INDEX, /* 0x00060001, invalid L2 Hash index */
|
||||
RT_ERR_L2_CAM_INDEX, /* 0x00060002, invalid L2 CAM index */
|
||||
RT_ERR_L2_ENRTYSEL, /* 0x00060003, invalid EntrySel */
|
||||
RT_ERR_L2_INDEXTABLE_INDEX, /* 0x00060004, invalid L2 index table(=portMask table) index */
|
||||
RT_ERR_LIMITED_L2ENTRY_NUM, /* 0x00060005, invalid limited L2 entry number */
|
||||
RT_ERR_L2_AGGREG_PORT, /* 0x00060006, this aggregated port is not the lowest physical
|
||||
port of its aggregation group */
|
||||
RT_ERR_L2_FID, /* 0x00060007, invalid fid */
|
||||
RT_ERR_L2_RVID, /* 0x00060008, invalid cvid */
|
||||
RT_ERR_L2_NO_EMPTY_ENTRY, /* 0x00060009, no empty entry in L2 table */
|
||||
RT_ERR_L2_ENTRY_NOTFOUND, /* 0x0006000a, specified entry not found */
|
||||
RT_ERR_L2_INDEXTBL_FULL, /* 0x0006000b, the L2 index table is full */
|
||||
RT_ERR_L2_INVALID_FLOWTYPE, /* 0x0006000c, invalid L2 flow type */
|
||||
RT_ERR_L2_L2UNI_PARAM, /* 0x0006000d, invalid L2 unicast parameter */
|
||||
RT_ERR_L2_L2MULTI_PARAM, /* 0x0006000e, invalid L2 multicast parameter */
|
||||
RT_ERR_L2_IPMULTI_PARAM, /* 0x0006000f, invalid L2 ip multicast parameter */
|
||||
RT_ERR_L2_PARTIAL_HASH_KEY, /* 0x00060010, invalid L2 partial Hash key */
|
||||
RT_ERR_L2_EMPTY_ENTRY, /* 0x00060011, the entry is empty(invalid) */
|
||||
RT_ERR_L2_FLUSH_TYPE, /* 0x00060012, the flush type is invalid */
|
||||
RT_ERR_L2_NO_CPU_PORT, /* 0x00060013, CPU port not exist */
|
||||
|
||||
/* 0x0007xxxx for FILTER (PIE) */
|
||||
RT_ERR_FILTER_BLOCKNUM = 0x00070000, /* 0x00070000, invalid block number */
|
||||
RT_ERR_FILTER_ENTRYIDX, /* 0x00070001, invalid entry index */
|
||||
RT_ERR_FILTER_CUTLINE, /* 0x00070002, invalid cutline value */
|
||||
RT_ERR_FILTER_FLOWTBLBLOCK, /* 0x00070003, block belongs to flow table */
|
||||
RT_ERR_FILTER_INACLBLOCK, /* 0x00070004, block belongs to ingress ACL */
|
||||
RT_ERR_FILTER_ACTION, /* 0x00070005, action doesn't consist to entry type */
|
||||
RT_ERR_FILTER_INACL_RULENUM, /* 0x00070006, invalid ACL rulenum */
|
||||
RT_ERR_FILTER_INACL_TYPE, /* 0x00070007, entry type isn't an ingress ACL rule */
|
||||
RT_ERR_FILTER_INACL_EXIST, /* 0x00070008, ACL entry is already exit */
|
||||
RT_ERR_FILTER_INACL_EMPTY, /* 0x00070009, ACL entry is empty */
|
||||
RT_ERR_FILTER_FLOWTBL_TYPE, /* 0x0007000a, entry type isn't an flow table rule */
|
||||
RT_ERR_FILTER_FLOWTBL_RULENUM, /* 0x0007000b, invalid flow table rulenum */
|
||||
RT_ERR_FILTER_FLOWTBL_EMPTY, /* 0x0007000c, flow table entry is empty */
|
||||
RT_ERR_FILTER_FLOWTBL_EXIST, /* 0x0007000d, flow table entry is already exist */
|
||||
RT_ERR_FILTER_METER_ID, /* 0x0007000e, invalid metering id */
|
||||
RT_ERR_FILTER_LOG_ID, /* 0x0007000f, invalid log id */
|
||||
RT_ERR_FILTER_INACL_ACT_NOT_SUPPORT, /* 0x00070010, action not support */
|
||||
RT_ERR_FILTER_INACL_RULE_NOT_SUPPORT, /* 0x00070011, rule not support */
|
||||
|
||||
/* 0x0008xxxx for ACL Rate Limit */
|
||||
RT_ERR_ACLRL_HTHR = 0x00080000, /* 0x00080000, invalid high threshold */
|
||||
RT_ERR_ACLRL_TIMESLOT, /* 0x00080001, invalid time slot */
|
||||
RT_ERR_ACLRL_TOKEN, /* 0x00080002, invalid token amount */
|
||||
RT_ERR_ACLRL_RATE, /* 0x00080003, invalid rate */
|
||||
|
||||
/* 0x0009xxxx for Link aggregation */
|
||||
RT_ERR_LA_CPUPORT = 0x00090000, /* 0x00090000, CPU port can not be aggregated port */
|
||||
RT_ERR_LA_TRUNK_ID, /* 0x00090001, invalid trunk id */
|
||||
RT_ERR_LA_PORTMASK, /* 0x00090002, invalid port mask */
|
||||
RT_ERR_LA_HASHMASK, /* 0x00090003, invalid hash mask */
|
||||
RT_ERR_LA_DUMB, /* 0x00090004, this API should be used in 802.1ad dumb mode */
|
||||
RT_ERR_LA_PORTNUM_DUMB, /* 0x00090005, it can only aggregate at most four ports when 802.1ad dumb mode */
|
||||
RT_ERR_LA_PORTNUM_NORMAL, /* 0x00090006, it can only aggregate at most eight ports when 802.1ad normal mode */
|
||||
RT_ERR_LA_MEMBER_OVERLAP, /* 0x00090007, the specified port mask is overlapped with other group */
|
||||
RT_ERR_LA_NOT_MEMBER_PORT, /* 0x00090008, the port is not a member port of the trunk */
|
||||
RT_ERR_LA_TRUNK_NOT_EXIST, /* 0x00090009, the trunk doesn't exist */
|
||||
|
||||
|
||||
/* 0x000axxxx for storm filter */
|
||||
RT_ERR_SFC_TICK_PERIOD = 0x000a0000, /* 0x000a0000, invalid SFC tick period */
|
||||
RT_ERR_SFC_UNKNOWN_GROUP, /* 0x000a0001, Unknown Storm filter group */
|
||||
|
||||
/* 0x000bxxxx for pattern match */
|
||||
RT_ERR_PM_MASK = 0x000b0000, /* 0x000b0000, invalid pattern length. Pattern length should be 8 */
|
||||
RT_ERR_PM_LENGTH, /* 0x000b0001, invalid pattern match mask, first byte must care */
|
||||
RT_ERR_PM_MODE, /* 0x000b0002, invalid pattern match mode */
|
||||
|
||||
/* 0x000cxxxx for input bandwidth control */
|
||||
RT_ERR_INBW_TICK_PERIOD = 0x000c0000, /* 0x000c0000, invalid tick period for input bandwidth control */
|
||||
RT_ERR_INBW_TOKEN_AMOUNT, /* 0x000c0001, invalid amount of token for input bandwidth control */
|
||||
RT_ERR_INBW_FCON_VALUE, /* 0x000c0002, invalid flow control ON threshold value for input bandwidth control */
|
||||
RT_ERR_INBW_FCOFF_VALUE, /* 0x000c0003, invalid flow control OFF threshold value for input bandwidth control */
|
||||
RT_ERR_INBW_FC_ALLOWANCE, /* 0x000c0004, invalid allowance of incomming packet for input bandwidth control */
|
||||
RT_ERR_INBW_RATE, /* 0x000c0005, invalid input bandwidth */
|
||||
|
||||
/* 0x000dxxxx for QoS */
|
||||
RT_ERR_QOS_1P_PRIORITY = 0x000d0000, /* 0x000d0000, invalid 802.1P priority */
|
||||
RT_ERR_QOS_DSCP_VALUE, /* 0x000d0001, invalid DSCP value */
|
||||
RT_ERR_QOS_INT_PRIORITY, /* 0x000d0002, invalid internal priority */
|
||||
RT_ERR_QOS_SEL_DSCP_PRI, /* 0x000d0003, invalid DSCP selection priority */
|
||||
RT_ERR_QOS_SEL_PORT_PRI, /* 0x000d0004, invalid port selection priority */
|
||||
RT_ERR_QOS_SEL_IN_ACL_PRI, /* 0x000d0005, invalid ingress ACL selection priority */
|
||||
RT_ERR_QOS_SEL_CLASS_PRI, /* 0x000d0006, invalid classifier selection priority */
|
||||
RT_ERR_QOS_EBW_RATE, /* 0x000d0007, invalid egress bandwidth rate */
|
||||
RT_ERR_QOS_SCHE_TYPE, /* 0x000d0008, invalid QoS scheduling type */
|
||||
RT_ERR_QOS_QUEUE_WEIGHT, /* 0x000d0009, invalid Queue weight */
|
||||
RT_ERR_QOS_SEL_PRI_SOURCE, /* 0x000d000a, invalid selection of priority source */
|
||||
|
||||
/* 0x000exxxx for port ability */
|
||||
RT_ERR_PHY_PAGE_ID = 0x000e0000, /* 0x000e0000, invalid PHY page id */
|
||||
RT_ERR_PHY_REG_ID, /* 0x000e0001, invalid PHY reg id */
|
||||
RT_ERR_PHY_DATAMASK, /* 0x000e0002, invalid PHY data mask */
|
||||
RT_ERR_PHY_AUTO_NEGO_MODE, /* 0x000e0003, invalid PHY auto-negotiation mode*/
|
||||
RT_ERR_PHY_SPEED, /* 0x000e0004, invalid PHY speed setting */
|
||||
RT_ERR_PHY_DUPLEX, /* 0x000e0005, invalid PHY duplex setting */
|
||||
RT_ERR_PHY_FORCE_ABILITY, /* 0x000e0006, invalid PHY force mode ability parameter */
|
||||
RT_ERR_PHY_FORCE_1000, /* 0x000e0007, invalid PHY force mode 1G speed setting */
|
||||
RT_ERR_PHY_TXRX, /* 0x000e0008, invalid PHY tx/rx */
|
||||
RT_ERR_PHY_RTCT_NOT_FINISH, /* 0x000e0009, PHY RTCT in progress */
|
||||
|
||||
/* 0x000fxxxx for mirror */
|
||||
RT_ERR_MIRROR_DIRECTION = 0x000f0000, /* 0x000f0000, invalid error mirror direction */
|
||||
RT_ERR_MIRROR_SESSION_FULL, /* 0x000f0001, mirroring session is full */
|
||||
RT_ERR_MIRROR_SESSION_NOEXIST, /* 0x000f0002, mirroring session not exist */
|
||||
RT_ERR_MIRROR_PORT_EXIST, /* 0x000f0003, mirroring port already exists */
|
||||
RT_ERR_MIRROR_PORT_NOT_EXIST, /* 0x000f0004, mirroring port does not exists */
|
||||
RT_ERR_MIRROR_PORT_FULL, /* 0x000f0005, Exceeds maximum number of supported mirroring port */
|
||||
|
||||
/* 0x0010xxxx for stat */
|
||||
RT_ERR_STAT_INVALID_GLOBAL_CNTR = 0x00100000, /* 0x00100000, Invalid Global Counter */
|
||||
RT_ERR_STAT_INVALID_PORT_CNTR, /* 0x00100001, Invalid Port Counter */
|
||||
RT_ERR_STAT_GLOBAL_CNTR_FAIL, /* 0x00100002, Could not retrieve/reset Global Counter */
|
||||
RT_ERR_STAT_PORT_CNTR_FAIL, /* 0x00100003, Could not retrieve/reset Port Counter */
|
||||
|
||||
/* 0x0011xxxx for dot1x */
|
||||
RT_ERR_DOT1X_INVALID_DIRECTION = 0x00110000, /* 0x00110000, Invalid Authentication Direction */
|
||||
RT_ERR_DOT1X_PORTBASEDPNEN, /* 0x00110001, Port-based enable port error */
|
||||
RT_ERR_DOT1X_PORTBASEDAUTH, /* 0x00110002, Port-based auth port error */
|
||||
RT_ERR_DOT1X_PORTBASEDOPDIR, /* 0x00110003, Port-based opdir error */
|
||||
RT_ERR_DOT1X_MACBASEDPNEN, /* 0x00110004, MAC-based enable port error */
|
||||
RT_ERR_DOT1X_MACBASEDOPDIR, /* 0x00110005, MAC-based opdir error */
|
||||
RT_ERR_DOT1X_PROC, /* 0x00110006, unauthorized behavior error */
|
||||
RT_ERR_DOT1X_GVLANIDX, /* 0x00110007, guest vlan index error */
|
||||
RT_ERR_DOT1X_GVLANTALK, /* 0x00110008, guest vlan OPDIR error */
|
||||
RT_ERR_DOT1X_MAC_PORT_MISMATCH, /* 0x00110009, Auth MAC and port mismatch eror */
|
||||
|
||||
RT_ERR_END /* The symbol is the latest symbol */
|
||||
} rt_error_code_t;
|
||||
|
||||
|
||||
#endif /* __COMMON_RT_ERROR_H__ */
|
||||
|
|
@ -0,0 +1,96 @@
|
|||
#ifndef _RTK_TYPES_H_
|
||||
#define _RTK_TYPES_H_
|
||||
|
||||
typedef unsigned long long uint64;
|
||||
typedef long long int64;
|
||||
typedef unsigned long uint32;
|
||||
typedef long int32;
|
||||
typedef unsigned short uint16;
|
||||
typedef short int16;
|
||||
typedef unsigned char uint8;
|
||||
typedef char int8;
|
||||
|
||||
typedef uint32 ipaddr_t;
|
||||
typedef uint32 memaddr;
|
||||
|
||||
#ifndef ETHER_ADDR_LEN
|
||||
#define ETHER_ADDR_LEN 6
|
||||
#endif
|
||||
|
||||
typedef struct ether_addr_s
|
||||
{
|
||||
uint8 octet[ETHER_ADDR_LEN];
|
||||
} ether_addr_t;
|
||||
|
||||
#define swapl32(x) \
|
||||
((((x)&0xff000000U) >> 24) | \
|
||||
(((x)&0x00ff0000U) >> 8) | \
|
||||
(((x)&0x0000ff00U) << 8) | \
|
||||
(((x)&0x000000ffU) << 24))
|
||||
#define swaps16(x) \
|
||||
((((x)&0xff00) >> 8) | \
|
||||
(((x)&0x00ff) << 8))
|
||||
|
||||
#ifdef LITTLE_ENDIAN
|
||||
#ifndef _LITTLE_ENDIAN
|
||||
#define _LITTLE_ENDIAN //
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef ntohs
|
||||
#ifdef LITTLE_ENDIAN
|
||||
#define ntohs(x) (swaps16(x))
|
||||
#define ntohl(x) (swapl32(x))
|
||||
#define htons(x) (swaps16(x))
|
||||
#define htonl(x) (swapl32(x))
|
||||
#else
|
||||
#define ntohs(x) (x)
|
||||
#define ntohl(x) (x)
|
||||
#define htons(x) (x)
|
||||
#define htonl(x) (x)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef LITTLE_ENDIAN
|
||||
#define MEM16(x) (x)
|
||||
#else
|
||||
#define MEM16(x) (swaps16(x))
|
||||
#endif
|
||||
|
||||
/* type abstraction */
|
||||
|
||||
typedef int32 rtk_api_ret_t;
|
||||
typedef int32 ret_t;
|
||||
typedef uint64 rtk_u_long_t;
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0
|
||||
#endif
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE 1
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
#define FALSE 0
|
||||
#endif
|
||||
|
||||
#ifndef SUCCESS
|
||||
#define SUCCESS 0
|
||||
#endif
|
||||
|
||||
#ifndef FAILED
|
||||
#define FAILED -1
|
||||
#endif
|
||||
|
||||
#if 0 //
|
||||
#ifdef __KERNEL__
|
||||
#define rtlglue_printf printk
|
||||
#else
|
||||
#define rtlglue_printf printf
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define rtlglue_printf os_printf
|
||||
|
||||
#endif /* _RTL8370_TYPES_H_ */
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
#ifndef _RTL8370_ASICDRV_H_
|
||||
#define _RTL8370_ASICDRV_H_
|
||||
|
||||
#include <rtk_types.h>
|
||||
#include <rtl8370_reg.h>
|
||||
#include <rtl8370_base.h>
|
||||
#include <rtk_error.h>
|
||||
|
||||
#define RTL8370_REGBITLENGTH 16
|
||||
#define RTL8370_REGDATAMAX 0xFFFF
|
||||
|
||||
#define RTL8370_VIDMAX 0xFFF
|
||||
#define RTL8370_EVIDMAX 0x1FFF
|
||||
#define RTL8370_CVLANMCNO 32
|
||||
#define RTL8370_CVIDXMAX (RTL8370_CVLANMCNO - 1)
|
||||
|
||||
#define RTL8370_PRIMAX 7
|
||||
|
||||
#define RTL8370_PRIDECMAX 0xFF
|
||||
|
||||
#define RTL8370_PORTNO 16
|
||||
#define RTL8370_PORTIDMAX (RTL8370_PORTNO - 1)
|
||||
#define RTL8370_PMSKMAX ((1 << (RTL8370_PORTNO)) - 1)
|
||||
#define RTL8370_PORTMASK 0xFFFF
|
||||
|
||||
#define RTL8370_SVIDXNO 64
|
||||
#define RTL8370_SVIDXMAX (RTL8370_SVIDXNO - 1)
|
||||
#define RTL8370_MSTIMAX 15
|
||||
|
||||
#define RTL8370_METERNO 64
|
||||
#define RTL8370_METERMAX (RTL8370_METERNO - 1)
|
||||
|
||||
#define RTL8370_QUEUENO 8
|
||||
#define RTL8370_QIDMAX (RTL8370_QUEUENO - 1)
|
||||
|
||||
#define RTL8370_PHY_BUSY_CHECK_COUNTER 1000
|
||||
#define RTL8370_PHYNO 8
|
||||
#define RTL8370_PHYIDMAX (RTL8370_PHYNO - 1)
|
||||
|
||||
#define RTL8370_QOS_GRANULARTY_MAX 0x1FFFF
|
||||
#define RTL8370_QOS_GRANULARTY_LSB_MASK 0xFFFF
|
||||
#define RTL8370_QOS_GRANULARTY_LSB_OFFSET 0
|
||||
#define RTL8370_QOS_GRANULARTY_MSB_MASK 0x10000
|
||||
#define RTL8370_QOS_GRANULARTY_MSB_OFFSET 16
|
||||
|
||||
#define RTL8370_QOS_GRANULARTY_UNIT_KBPS 8
|
||||
|
||||
#define RTL8370_QOS_RATE_INPUT_MAX (0x1FFFF * 8)
|
||||
#define RTL8370_QOS_RATE_INPUT_MIN 8
|
||||
|
||||
#define RTL8370_QUEUE_MASK 0xFF
|
||||
|
||||
#define RTL8370_EFIDMAX 0x7
|
||||
#define RTL8370_FIDMAX 0xFFF
|
||||
|
||||
/* the above macro is generated by genDotH */
|
||||
#define RTL8370_VALID_REG_NO 3236
|
||||
|
||||
/*=======================================================================
|
||||
* Enum
|
||||
*========================================================================*/
|
||||
enum RTL8370_TABLE_ACCESS_OP
|
||||
{
|
||||
TB_OP_READ = 0,
|
||||
TB_OP_WRITE
|
||||
};
|
||||
|
||||
enum RTL8370_TABLE_ACCESS_TARGET
|
||||
{
|
||||
TB_TARGET_ACLRULE = 1,
|
||||
TB_TARGET_ACLACT,
|
||||
TB_TARGET_CVLAN,
|
||||
TB_TARGET_L2
|
||||
};
|
||||
|
||||
#define RTL8370_TABLE_ACCESS_REG_DATA(op, target) ((op << 4) | target)
|
||||
|
||||
/*=======================================================================
|
||||
* Structures
|
||||
*========================================================================*/
|
||||
|
||||
typedef struct smi_ether_addr_s
|
||||
{
|
||||
|
||||
#ifdef _LITTLE_ENDIAN
|
||||
uint16 mac0 : 8;
|
||||
uint16 mac1 : 8;
|
||||
uint16 mac2 : 8;
|
||||
uint16 mac3 : 8;
|
||||
uint16 mac4 : 8;
|
||||
uint16 mac5 : 8;
|
||||
#else
|
||||
uint16 mac1 : 8;
|
||||
uint16 mac0 : 8;
|
||||
uint16 mac3 : 8;
|
||||
uint16 mac2 : 8;
|
||||
uint16 mac5 : 8;
|
||||
uint16 mac4 : 8;
|
||||
#endif
|
||||
|
||||
} smi_ether_addr_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
extern ret_t rtl8370_setAsicRegBit(uint16 reg, int bitNum, uint16 value);
|
||||
extern ret_t rtl8370_getAsicRegBit(uint16 reg, int bitNum, uint16 *value);
|
||||
|
||||
extern ret_t rtl8370_setAsicRegBits(uint16 reg, int bits, uint16 value);
|
||||
extern ret_t rtl8370_getAsicRegBits(uint16 reg, int bits, uint16 *value);
|
||||
|
||||
extern ret_t rtl8370_setAsicReg(uint16 reg, uint16 value);
|
||||
extern ret_t rtl8370_getAsicReg(uint16 reg, uint16 *value);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*#ifndef _RTL8370_ASICDRV_H_*/
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
#ifndef _RTL8370_ASICDRV_PHY_H_
|
||||
#define _RTL8370_ASICDRV_PHY_H_
|
||||
|
||||
#define RTL8370_PHY_INTERNALNOMAX 0x7
|
||||
#define RTL8370_PHY_REGNOMAX 0x1F
|
||||
#define RTL8370_PHY_EXTERNALMAX 0x7
|
||||
|
||||
#define RTL8370_PHY_BASE 0x2000
|
||||
#define RTL8370_PHY_EXT_BASE 0xA000
|
||||
|
||||
#define RTL8370_PHY_OFFSET 5
|
||||
#define RTL8370_PHY_EXT_OFFSET 9
|
||||
#define RTL8370_PHY_EXTLED_OFFSET 8
|
||||
|
||||
#define RTL8370_PHY_PAGE_ADDRESS 31
|
||||
|
||||
extern ret_t rtl8370_setAsicPHYReg(int phyNo, int phyAddr, uint16 data);
|
||||
extern ret_t rtl8370_getAsicPHYReg(int phyNo, int phyAddr, uint16 *data);
|
||||
|
||||
#endif /*#ifndef _RTL8370_ASICDRV_PHY_H_*/
|
||||
|
|
@ -0,0 +1,628 @@
|
|||
#ifndef _RTL8370_BASE_H_
|
||||
#define _RTL8370_BASE_H_
|
||||
|
||||
#include <rtl8370_reg.h>
|
||||
|
||||
/* (16'h0000) port_reg */
|
||||
|
||||
#define RTL8370_PORT_SPECIAL_CONGEST_MODE_TIMER_BASE RTL8370_REG_PORT0_MISC_CFG
|
||||
#define RTL8370_PORT_SPECIAL_CONGEST_MODE_TIMER_REG(port) (RTL8370_PORT_SPECIAL_CONGEST_MODE_TIMER_BASE + (port << 5))
|
||||
#define RTL8370_PORT_SPECIAL_CONGEST_MODE_TIMER_OFFSET RTL8370_PORT0_MISC_CFG_TIMER_OFFSET
|
||||
#define RTL8370_PORT_SPECIAL_CONGEST_MODE_TIMER_MASK RTL8370_PORT0_MISC_CFG_TIMER_MASK
|
||||
|
||||
#define RTL8370_PORT_MISC_CFG_BASE RTL8370_REG_PORT0_MISC_CFG
|
||||
#define RTL8370_PORT_MISC_CFG_REG(port) (RTL8370_PORT_MISC_CFG_BASE + (port << 5))
|
||||
#define RTL8370_INGRESSBW_PORT_FLOWCRTL_ENABLE_OFFSET RTL8370_INGRESSBW_PORT0_FLOWCRTL_OFFSET
|
||||
#define RTL8370_INGRESSBW_PORT_FLOWCRTL_ENABLE_MASK RTL8370_INGRESSBW_PORT0_FLOWCRTL_MASK
|
||||
#define RTL8370_INGRESSBW_PORT_IFG_OFFSET RTL8370_INGRESSBW_PORT0_IFG_OFFSET
|
||||
#define RTL8370_INGRESSBW_PORT_IFG_MASK RTL8370_INGRESSBW_PORT0_IFG_MASK
|
||||
#define RTL8370_VLAN_EGRESS_MDOE_OFFSET RTL8370_VLAN_PORT0_EGRESS_MODE_OFFSET
|
||||
#define RTL8370_VLAN_EGRESS_MDOE_MASK RTL8370_VLAN_PORT0_EGRESS_MODE_MASK
|
||||
#define RTL8370_SPECIALCONGEST_SUSTAIN_TIMER_OFFSET RTL8370_CONGESTION_PORT0_SUSTAIN_TIME_OFFSET
|
||||
#define RTL8370_SPECIALCONGEST_SUSTAIN_TIMER_MASK RTL8370_CONGESTION_PORT0_SUSTAIN_TIME_MASK
|
||||
|
||||
#define RTL8370_INGRESSBW_PORT_RATE_LSB_BASE RTL8370_REG_INGRESSBW_PORT0_RATE_CRTL0
|
||||
#define RTL8370_INGRESSBW_PORT_RATE_LSB_REG(port) (RTL8370_INGRESSBW_PORT_RATE_LSB_BASE + (port << 5))
|
||||
|
||||
#define RTL8370_INGRESSBW_PORT_RATE_MSB_BASE RTL8370_REG_INGRESSBW_PORT0_RATE_CRTL1
|
||||
#define RTL8370_INGRESSBW_PORT_RATE_MSB_REG(port) (RTL8370_INGRESSBW_PORT_RATE_MSB_BASE + (port << 5))
|
||||
|
||||
#define RTL8370_PORT_EEE_CFG_BASE RTL8370_REG_PORT0_EEECFG
|
||||
#define RTL8370_PORT_EEE_CFG_REG(port) (RTL8370_REG_PORT0_EEECFG + (port << 5))
|
||||
#define RTL8370_PORT_EEE_TX_ENABLE_OFFSET RTL8370_PORT0_EEECFG_EEE_TX_OFFSET
|
||||
#define RTL8370_PORT_EEE_TX_ENABLE_MASK RTL8370_PORT0_EEECFG_EEE_TX_MASK
|
||||
#define RTL8370_PORT_EEE_RX_ENABLE_OFFSET RTL8370_PORT0_EEECFG_EEE_RX_OFFSET
|
||||
#define RTL8370_PORT_EEE_RX_ENABLE_MASK RTL8370_PORT0_EEECFG_EEE_RX_MASK
|
||||
#define RTL8370_PORT_EEE_FORCE_OFFSET RTL8370_PORT0_EEECFG_EEE_FORCE_OFFSET
|
||||
#define RTL8370_PORT_EEE_FORCE_MASK RTL8370_PORT0_EEECFG_EEE_FORCE_MASK
|
||||
#define RTL8370_PORT_EEE_100M_OFFSET RTL8370_PORT0_EEECFG_EEE_100M_OFFSET
|
||||
#define RTL8370_PORT_EEE_100M_MASK RTL8370_PORT0_EEECFG_EEE_100M_MASK
|
||||
#define RTL8370_PORT_EEE_GIGA_OFFSET RTL8370_PORT0_EEECFG_EEE_GIGA_OFFSET
|
||||
#define RTL8370_PORT_EEE_GIGA_MASK RTL8370_PORT0_EEECFG_EEE_GIGA_MASK
|
||||
#define RTL8370_PORT_EEE_LPI_STATUS_OFFSET RTL8370_PORT0_EEECFG_EEE_LPI_OFFSET
|
||||
#define RTL8370_PORT_EEE_LPI_STATUS_MASK RTL8370_PORT0_EEECFG_EEE_LPI_MASK
|
||||
#define RTL8370_PORT_EEE_TX_LPI_STATUS_OFFSET RTL8370_PORT0_EEECFG_EEE_TX_LPI_OFFSET
|
||||
#define RTL8370_PORT_EEE_TX_LPI_STATUS_MASK RTL8370_PORT0_EEECFG_EEE_TX_LPI_MASK
|
||||
#define RTL8370_PORT_EEE_RX_LPI_STATUS_OFFSET RTL8370_PORT0_EEECFG_EEE_RX_LPI_OFFSET
|
||||
#define RTL8370_PORT_EEE_RX_LPI_STATUS_MASK RTL8370_PORT0_EEECFG_EEE_RX_LPI_MASK
|
||||
#define RTL8370_PORT_EEE_PAUSE_INDICATOR_OFFSET RTL8370_PORT0_EEECFG_EEE_PAUSE_INDICATOR_OFFSET
|
||||
#define RTL8370_PORT_EEE_PAUSE_INDICATOR_MASK RTL8370_PORT0_EEECFG_EEE_PAUSE_INDICATOR_MASK
|
||||
#define RTL8370_PORT_EEE_WAKE_REQ_OFFSET RTL8370_PORT0_EEECFG_EEE_WAKE_REQ_OFFSET
|
||||
#define RTL8370_PORT_EEE_WAKE_REQ_MASK RTL8370_PORT0_EEECFG_EEE_WAKE_REQ_MASK
|
||||
|
||||
#define RTL8370_PORT_EEE_TX_METER_BASE RTL8370_REG_P0EEETXMTR
|
||||
#define RTL8370_PORT_EEE_TX_METER_REG(port) (RTL8370_REG_P0EEETXMTR + (port << 5))
|
||||
#define RTL8370_PORT_EEE_RX_METER_BASE RTL8370_REG_P0EEERXMTR
|
||||
#define RTL8370_PORT_EEE_RX_METER_REG(port) (RTL8370_REG_P0EEERXMTR + (port << 5))
|
||||
|
||||
|
||||
#define RTL8370_PORT_EEEP_TX_ENABLE_OFFSET RTL8370_PORT0_EEECFG_EEEP_ENABLE_TX_OFFSET
|
||||
#define RTL8370_PORT_EEEP_TX_ENABLE_MASK RTL8370_PORT0_EEECFG_EEEP_ENABLE_TX_MASK
|
||||
#define RTL8370_PORT_EEEP_RX_ENABLE_OFFSET RTL8370_PORT0_EEECFG_EEEP_ENABLE_RX_OFFSET
|
||||
#define RTL8370_PORT_EEEP_RX_ENABLE_MASK RTL8370_PORT0_EEECFG_EEEP_ENABLE_RX_MASK
|
||||
#define RTL8370_PORT_EEEP_SLEEP_REQ_OFFSET RTL8370_PORT0_EEECFG_EEE_SLEEP_REQ_OFFSET
|
||||
#define RTL8370_PORT_EEEP_SLEEP_REQ_MASK RTL8370_PORT0_EEECFG_EEE_SLEEP_REQ_MASK
|
||||
|
||||
/* (16'h0200) outq_reg */
|
||||
|
||||
#define RTL8370_FLOWCTRL_QUEUE_DROP_ON_BASE RTL8370_REG_FLOWCTRL_QUEUE0_DROP_ON
|
||||
#define RTL8370_FLOWCTRL_QUEUE_DROP_ON_REG(queue) (RTL8370_FLOWCTRL_QUEUE_DROP_ON_BASE + queue)
|
||||
#define RTL8370_FLOWCTRL_QUEUE_DROP_ON_OFFSET RTL8370_FLOWCTRL_QUEUE0_DROP_ON_OFFSET
|
||||
#define RTL8370_FLOWCTRL_QUEUE_DROP_ON_MASK RTL8370_FLOWCTRL_QUEUE0_DROP_ON_MASK
|
||||
|
||||
#define RTL8370_FLOWCTRL_PORT_DROP_ON_BASE RTL8370_REG_FLOWCTRL_PORT0_DROP_ON
|
||||
#define RTL8370_FLOWCTRL_PORT_DROP_ON_REG(PORT) (RTL8370_FLOWCTRL_PORT_DROP_ON_BASE + PORT)
|
||||
#define RTL8370_FLOWCTRL_PORT_DROP_ON_OFFSET RTL8370_FLOWCTRL_PORT0_DROP_ON_OFFSET
|
||||
#define RTL8370_FLOWCTRL_PORT_DROP_ON_MASK RTL8370_FLOWCTRL_PORT0_DROP_ON_MASK
|
||||
|
||||
#define RTL8370_FLOWCTRL_PORT_GAP_REG RTL8370_REG_FLOWCTRL_PORT_GAP
|
||||
#define RTL8370_FLOWCTRL_QUEUE_GAP_REG RTL8370_REG_FLOWCTRL_QUEUE_GAP
|
||||
#define RTL8370_FLOWCTRL_PORT_QEMPTY_REG RTL8370_REG_PORT_QEMPTY
|
||||
|
||||
/* (16'h0300) sch_reg */
|
||||
|
||||
#define RTL8370_SCHEDULE_WFQ_BURST_SIZE_REG RTL8370_REG_SCHEDULE_WFQ_BURST_SIZE
|
||||
|
||||
#define RTL8370_SCHEDULE_QUEUE_TYPE_BASE RTL8370_REG_SCHEDULE_QUEUE_TYPE_CTRL0
|
||||
#define RTL8370_SCHEDULE_QUEUE_TYPE_REG(port) (RTL8370_SCHEDULE_QUEUE_TYPE_BASE + (port >> 1))
|
||||
#define RTL8370_SCHEDULE_QUEUE_TYPE_OFFSET(port, queue) (((port & 0x1) << 3) + queue)
|
||||
#define RTL8370_SCHEDULE_QUEUE_TYPE_MASK(port, queue) RTL8370_SCHEDULE_QUEUE_TYPE_OFFSET(port, queue)
|
||||
|
||||
#define RTL8370_SCHEDULE_PORT_QUEUE_WFQ_WEIGHT_BASE RTL8370_REG_SCHEDULE_PORT0_QUEUE0_WFQ_WEIGHT
|
||||
#define RTL8370_SCHEDULE_PORT_QUEUE_WFQ_WEIGHT_REG(port, queue) (RTL8370_SCHEDULE_PORT_QUEUE_WFQ_WEIGHT_BASE + (port << 3) + queue)
|
||||
#define RTL8370_SCHEDULE_PORT_QUEUE_WFQ_WEIGHT_OFFSET RTL8370_SCHEDULE_PORT0_QUEUE0_WFQ_WEIGHT_OFFSET
|
||||
#define RTL8370_SCHEDULE_PORT_QUEUE_WFQ_WEIGHT_MASK RTL8370_SCHEDULE_PORT0_QUEUE0_WFQ_WEIGHT_MASK
|
||||
|
||||
#define RTL8370_SCHEDULE_APR_CRTL_REG RTL8370_REG_SCHEDULE_APR_CRTL0
|
||||
#define RTL8370_SCHEDULE_APR_CRTL_OFFSET(port) (port)
|
||||
#define RTL8370_SCHEDULE_APR_CRTL_MASK(port) (1 << RTL8370_SCHEDULE_APR_CRTL_OFFSET(port))
|
||||
|
||||
#define RTL8370_SCHEDULE_PORT_APR_METER_BASE RTL8370_REG_SCHEDULE_PORT0_APR_METER_CTRL0
|
||||
#define RTL8370_SCHEDULE_PORT_APR_METER_REG(port, queue) (RTL8370_SCHEDULE_PORT_APR_METER_BASE + (port << 2) + (queue / 5))
|
||||
#define RTL8370_SCHEDULE_PORT_APR_METER_OFFSET(queue) (3 * (queue % 5))
|
||||
#define RTL8370_SCHEDULE_PORT_APR_METER_MASK(queue) (RTL8370_PORT0_QUEUE0_APR_METER_MASK << RTL8370_SCHEDULE_PORT_APR_METER_OFFSET(queue))
|
||||
|
||||
#define RTL8370_PORT_EGRESSBW_LSB_BASE RTL8370_REG_PORT0_EGRESSBW_CTRL0
|
||||
#define RTL8370_PORT_EGRESSBW_LSB_REG(port) (RTL8370_PORT_EGRESSBW_LSB_BASE + (port << 1))
|
||||
|
||||
#define RTL8370_PORT_EGRESSBW_MSB_BASE RTL8370_REG_PORT0_EGRESSBW_CTRL1
|
||||
#define RTL8370_PORT_EGRESSBW_MSB_REG(port) (RTL8370_PORT_EGRESSBW_MSB_BASE + (port << 1))
|
||||
#define RTL8370_PORT_EGRESSBW_MSB_OFFSET RTL8370_PORT0_EGRESSBW_CTRL1_OFFSET
|
||||
#define RTL8370_PORT_EGRESSBW_MSB_MASK RTL8370_PORT0_EGRESSBW_CTRL1_MASK
|
||||
|
||||
/* (16'h0500) table_reg */
|
||||
|
||||
#define RTL8370_TABLE_ACCESS_CTRL_REG RTL8370_REG_TABLE_ACCESS_CTRL
|
||||
|
||||
#define RTL8370_TABLE_ACCESS_ADDR_REG RTL8370_REG_TABLE_ACCESS_ADDR
|
||||
|
||||
#define RTL8370_TABLE_ACCESS_DATA_BASE RTL8370_REG_TABLE_ACCESS_DATA0
|
||||
#define RTL8370_TABLE_ACCESS_DATA_REG(index) (RTL8370_TABLE_ACCESS_DATA_BASE + index)
|
||||
|
||||
/* (16'h0600) acl_reg */
|
||||
|
||||
#define RTL8370_ACL_RULE_TEMPLATE_CRTL_BASE RTL8370_REG_ACL_RULE_TEMPLATE0_CRTL0
|
||||
#define RTL8370_ACL_RULE_TEMPLATE_CTRL_REG(template, field) (RTL8370_ACL_RULE_TEMPLATE_CRTL_BASE + template * 0x4 + (field >> 1))
|
||||
#define RTL8370_ACL_TEMPLATE_FIELD_OFFSET(field) ((field & 0x01) <<3)
|
||||
#define RTL8370_ACL_TEMPLATE_FIELD_MASK(field) (0x3F << RTL8370_ACL_TEMPLATE_FIELD_OFFSET(field))
|
||||
|
||||
#define RTL8370_ACL_ACTION_CTRL_BASE RTL8370_REG_ACL_ACTION_CTRL0
|
||||
#define RTL8370_ACL_ACTION_CTRL_REG(rule) (RTL8370_ACL_ACTION_CTRL_BASE + (rule >> 1))
|
||||
#define RTL8370_ACL_OP_NOT_OFFSET(rule) (5 + ((rule & 0x1) << 3))
|
||||
#define RTL8370_ACL_OP_NOT_MASK(rule) (1 << RTL8370_ACL_OP_NOT_OFFSET(rule))
|
||||
#define RTL8370_ACL_OP_ACTION_OFFSET(rule) ((rule & 0x1) << 3)
|
||||
#define RTL8370_ACL_OP_ACTION_MASK(rule) (0x1F << RTL8370_ACL_OP_ACTION_OFFSET(rule))
|
||||
|
||||
#define RTL8370_ACL_ENABLE_REG RTL8370_REG_ACL_ENABLE
|
||||
#define RTL8370_ACL_UNMATCH_PERMIT_REG RTL8370_REG_ACL_UNMATCH_PERMIT
|
||||
|
||||
/* (16'h0700) cvlan_reg */
|
||||
|
||||
#define RTL8370_VLAN_PVID_CTRL_BASE RTL8370_REG_VLAN_PVID_CTRL0
|
||||
#define RTL8370_VLAN_PVID_CTRL_REG(port) (RTL8370_VLAN_PVID_CTRL_BASE + (port >> 1))
|
||||
#define RTL8370_PORT_VIDX_OFFSET(port) ((port &1)<<3)
|
||||
#define RTL8370_PORT_VIDX_MASK(port) (RTL8370_PORT0_VIDX_MASK << RTL8370_PORT_VIDX_OFFSET(port))
|
||||
|
||||
#define RTL8370_VLAN_PPB_VALID_BASE RTL8370_REG_VLAN_PPB0_VALID
|
||||
#define RTL8370_VLAN_PPB_VALID_REG(item) (RTL8370_VLAN_PPB_VALID_BASE + (item << 3))
|
||||
|
||||
#define RTL8370_VLAN_PPB_CTRL_BASE RTL8370_REG_VLAN_PPB0_CTRL0
|
||||
#define RTL8370_VLAN_PPB_CTRL_REG(item, port) (RTL8370_VLAN_PPB_CTRL_BASE + (item << 3) + (port / 3) )
|
||||
#define RTL8370_VLAN_PPB_CTRL_OFFSET(port) ((port % 3) * 5)
|
||||
#define RTL8370_VLAN_PPB_CTRL_MASK(port) (RTL8370_PPB0_PORT0_INDEX_MASK << RTL8370_VLAN_PPB_CTRL_OFFSET(port))
|
||||
|
||||
#define RTL8370SG_VLAN_PPB_FRAMETYPE_BASE RTL8370_REG_VLAN_PPB0_CTRL5
|
||||
#define RTL8370SG_VLAN_PPB_FRAMETYPE_REG(item) (RTL8370SG_VLAN_PPB_FRAMETYPE_BASE + (item << 3))
|
||||
#define RTL8370SG_VLAN_PPB_FRAMETYPE_OFFSET RTL8370_PPB0_FRAME_TYPE_OFFSET
|
||||
#define RTL8370SG_VLAN_PPB_FRAMETYPE_MASK RTL8370_PPB0_FRAME_TYPE_MASK
|
||||
|
||||
#define RTL8370_VLAN_PPB_ETHERTYPR_BASE RTL8370_REG_VLAN_PPB0_CTRL6
|
||||
#define RTL8370_VLAN_PPB_ETHERTYPR_REG(item) (RTL8370_VLAN_PPB_ETHERTYPR_BASE + (item << 3))
|
||||
|
||||
#define RTL8370_VLAN_MEMBER_CONFIGURATION_BASE RTL8370_REG_VLAN_MEMBER_CONFIGURATION0_CTRL0
|
||||
|
||||
#define RTL8370_VLAN_FILTERING_REG RTL8370_REG_VLAN_CTRL
|
||||
#define RTL8370_VLAN_FILTERING_OFFSET RTL8370_VLAN_CTRL_OFFSET
|
||||
#define RTL8370_VLAN_FILTERING_MASK RTL8370_VLAN_CTRL_MASK
|
||||
|
||||
#define RTL8370_VLAN_CTRL_REG RTL8370_REG_VLAN_CTRL
|
||||
|
||||
#define RTL8370SG_VLAN_INGRESS_REG RTL8370_REG_VLAN_INGRESS
|
||||
|
||||
#define RTL8370_VLAN_ACCEPT_FRAME_TYPE_BASE RTL8370_REG_VLAN_ACCEPT_FRAME_TYPE_CTRL0
|
||||
#define RTL8370_VLAN_ACCEPT_FRAME_TYPE_REG(port) (RTL8370_VLAN_ACCEPT_FRAME_TYPE_BASE + (port >> 3))
|
||||
#define RTL8370_VLAN_ACCEPT_FRAME_TYPE_MASK(port) (RTL8370_VLAN_PORT0_FRAME_TYPE_MASK << ((port & 0x7) << 1))
|
||||
|
||||
#define RTL8370_PORT_EFID_BASE RTL8370_REG_PORT_EFID_CTRL0
|
||||
#define RTL8370_PORT_EFID_REG(port) (RTL8370_PORT_EFID_BASE + (port >> 2))
|
||||
#define RTL8370_PORT_EFID_OFFSET(port) ((port & 0x3) << 2)
|
||||
#define RTL8370_PORT_EFID_MASK(port) (RTL8370_PORT0_EFID_MASK << RTL8370_PORT_EFID_OFFSET(port))
|
||||
|
||||
#define RTL8370_PORT_PBFIDEN_REG RTL8370_REG_PORT_PBFIDEN
|
||||
|
||||
#define RTL8370_PORT_PBFID_BASE RTL8370_REG_PORT0_PBFID
|
||||
#define RTL8370_PORT_PBFID_REG(port) (RTL8370_PORT_PBFID_BASE + port)
|
||||
|
||||
/* (16'h0800) dpm_reg */
|
||||
|
||||
#define RTL8370_RMA_CTRL_BASE RTL8370_REG_RMA_CTRL00
|
||||
|
||||
#define RTL8370_IGMP_CTRL_REG RTL8370_REG_IGMP_CTRL
|
||||
|
||||
#define RTL8370_VLAN_PORTBASED_PRIORITY_BASE RTL8370_REG_VLAN_PORTBASED_PRIORITY_CTRL0
|
||||
#define RTL8370_VLAN_PORTBASED_PRIORITY_REG(port) (RTL8370_VLAN_PORTBASED_PRIORITY_BASE + (port >> 2))
|
||||
#define RTL8370_VLAN_PORTBASED_PRIORITY_OFFSET(port) ((port & 0x3) << 2)
|
||||
#define RTL8370_VLAN_PORTBASED_PRIORITY_MASK(port) (0x7 << RTL8370_VLAN_PORTBASED_PRIORITY_OFFSET(port))
|
||||
|
||||
#define RTL8370_VLAN_PPB_PRIORITY_ITEM_BASE RTL8370_REG_VLAN_PPB_PRIORITY_ITEM0_CTRL0
|
||||
#define RTL8370_VLAN_PPB_PRIORITY_ITEM_REG(port, item) (RTL8370_VLAN_PPB_PRIORITY_ITEM_BASE + (item << 2)+ (port>>2))
|
||||
#define RTL8370_VLAN_PPB_PRIORITY_ITEM_OFFSET(port) ((port & 0x3) <<2)
|
||||
#define RTL8370_VLAN_PPB_PRIORITY_ITEM_MASK(port) (RTL8370_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT0_PRIORITY_MASK << RTL8370_VLAN_PPB_PRIORITY_ITEM_OFFSET(port))
|
||||
|
||||
#define RTL8370_QOS_1Q_PRIORITY_REMAPPING_BASE RTL8370_REG_QOS_1Q_PRIORITY_REMAPPING_CTRL0
|
||||
#define RTL8370_QOS_1Q_PRIORITY_REMAPPING_REG(pri) (RTL8370_QOS_1Q_PRIORITY_REMAPPING_BASE + (pri >> 2))
|
||||
#define RTL8370_QOS_1Q_PRIORITY_REMAPPING_OFFSET(pri) ((pri & 0x3) << 2)
|
||||
#define RTL8370_QOS_1Q_PRIORITY_REMAPPING_MASK(pri) (0x7 << RTL8370_QOS_1Q_PRIORITY_REMAPPING_OFFSET(pri))
|
||||
|
||||
#define RTL8370_QOS_DSCP_TO_PRIORITY_BASE RTL8370_REG_QOS_DSCP_TO_PRIORITY_CTRL0
|
||||
#define RTL8370_QOS_DSCP_TO_PRIORITY_REG(dscp) (RTL8370_QOS_DSCP_TO_PRIORITY_BASE + (dscp >> 2))
|
||||
#define RTL8370_QOS_DSCP_TO_PRIORITY_OFFSET(dscp) ((dscp & 0x3) << 2)
|
||||
#define RTL8370_QOS_DSCP_TO_PRIORITY_MASK(dscp) (0x7 << RTL8370_QOS_DSCP_TO_PRIORITY_OFFSET(dscp))
|
||||
|
||||
#define RTL8370_QOS_PORTBASED_PRIORITY_BASE RTL8370_REG_QOS_PORTBASED_PRIORITY_CTRL0
|
||||
#define RTL8370_QOS_PORTBASED_PRIORITY_REG(port) (RTL8370_QOS_PORTBASED_PRIORITY_BASE + (port >> 2))
|
||||
#define RTL8370_QOS_PORTBASED_PRIORITY_OFFSET(port) ((port & 0x3) << 2)
|
||||
#define RTL8370_QOS_PORTBASED_PRIORITY_MASK(port) (0x7 << RTL8370_QOS_PORTBASED_PRIORITY_OFFSET(port))
|
||||
|
||||
#define RTL8370_QOS_INTERNAL_PRIORITY_DECISION_BASE RTL8370_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL0
|
||||
#define RTL8370_QOS_INTERNAL_PRIORITY_DECISION_REG(src) (RTL8370_QOS_INTERNAL_PRIORITY_DECISION_BASE + (src >> 1))
|
||||
#define RTL8370_QOS_INTERNAL_PRIORITY_DECISION_OFFSET(src) ((src & 1) << 3)
|
||||
#define RTL8370_QOS_INTERNAL_PRIORITY_DECISION_MASK(src) (RTL8370_QOS_PORT_WEIGHT_MASK << RTL8370_QOS_INTERNAL_PRIORITY_DECISION_OFFSET(src))
|
||||
|
||||
#define RTL8370_QOS_PRIPORITY_REMAPPING_IN_CPU_BASE RTL8370_REG_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0
|
||||
#define RTL8370_QOS_PRIPORITY_REMAPPING_IN_CPU_REG(pri) (RTL8370_QOS_PRIPORITY_REMAPPING_IN_CPU_BASE + (pri >> 2))
|
||||
#define RTL8370_QOS_PRIPORITY_REMAPPING_IN_CPU_OFFSET(pri) ((pri & 0x3) << 2)
|
||||
#define RTL8370_QOS_PRIPORITY_REMAPPING_IN_CPU_MASK(pri) (RTL8370_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY0_MASK << RTL8370_QOS_PRIPORITY_REMAPPING_IN_CPU_OFFSET(pri))
|
||||
|
||||
#define RTL8370SG_QOS_TRAP_PRIORITY_CTRL0_REG RTL8370_REG_QOS_TRAP_PRIORITY0
|
||||
|
||||
#define RTL8370SG_QOS_TRAP_PRIORITY_CTRL1_REG RTL8370_REG_QOS_TRAP_PRIORITY1
|
||||
|
||||
#define RTL8370_UNUCAST_FLOADING_PMSK_REG RTL8370_REG_UNUCAST_FLOADING_PMSK
|
||||
|
||||
#define RTL8370_UNMCAST_FLOADING_PMSK_REG RTL8370_REG_UNMCAST_FLOADING_PMSK
|
||||
|
||||
#define RTL8370_BCAST_FLOADING_PMSK_REG RTL8370_REG_BCAST_FLOADING_PMSK
|
||||
|
||||
#define RTL8370_PORT_ISOLATION_PORT_MASK_BASE RTL8370_REG_PORT_ISOLATION_PORT0_MASK
|
||||
#define RTL8370_PORT_ISOLATION_PORT_MASK_REG(port) (RTL8370_PORT_ISOLATION_PORT_MASK_BASE + port)
|
||||
|
||||
#define RTL8370_FORCE_CTRL_REG RTL8370_REG_FORCE_CTRL
|
||||
|
||||
#define RTL8370_SOURCE_PORT_BLOCK_REG RTL8370_REG_SOURCE_PORT_BLOCK
|
||||
|
||||
#define RTL8370_IPMCAST_VLAN_LEAKY_REG RTL8370_REG_IPMCAST_VLAN_LEAKY
|
||||
|
||||
#define RTL8370_IPMCAST_PORTISO_LEAKY_REG RTL8370_REG_IPMCAST_PORTISO_LEAKY
|
||||
|
||||
#define RTL8370_PORT_SECURIT_CTRL_REG RTL8370_REG_PORT_SECURITY_CTRL
|
||||
|
||||
#define RTL8370_UNKNOWN_IPV4_MULTICAST_BASE RTL8370_REG_UNKNOWN_IPV4_MULTICAST_CRTL0
|
||||
#define RTL8370_UNKNOWN_IPV4_MULTICAST_REG(port) (RTL8370_UNKNOWN_IPV4_MULTICAST_BASE + (port >> 3))
|
||||
#define RTL8370_UNKNOWN_IPV4_MULTICAST_OFFSET(port) ((port & 0x7) << 1)
|
||||
#define RTL8370_UNKNOWN_IPV4_MULTICAST_MASK(port) (RTL8370_PORT0_UNKNOWN_IP4_MCAST_MASK << RTL8370_UNKNOWN_IPV4_MULTICAST_OFFSET(port))
|
||||
|
||||
#define RTL8370_UNKNOWN_IPV6_MULTICAST_BASE RTL8370_REG_UNKNOWN_IPV6_MULTICAST_CRTL0
|
||||
#define RTL8370_UNKNOWN_IPV6_MULTICAST_REG(port) (RTL8370_UNKNOWN_IPV6_MULTICAST_BASE + (port >> 3))
|
||||
#define RTL8370_UNKNOWN_IPV6_MULTICAST_OFFSET(port) ((port & 0x7) << 1)
|
||||
#define RTL8370_UNKNOWN_IPV6_MULTICAST_MASK(port) (RTL8370_PORT0_UNKNOWN_IP4_MCAST_MASK << RTL8370_UNKNOWN_IPV6_MULTICAST_OFFSET(port))
|
||||
|
||||
#define RTL8370_UNKNOWN_L2_MULTICAST_BASE RTL8370_REG_UNKNOWN_L2_MULTICAST_CRTL0
|
||||
#define RTL8370_UNKNOWN_L2_MULTICAST_REG(port) (RTL8370_UNKNOWN_L2_MULTICAST_BASE + (port >> 3))
|
||||
#define RTL8370_UNKNOWN_L2_MULTICAST_OFFSET(port) ((port & 0x7) << 1)
|
||||
#define RTL8370_UNKNOWN_L2_MULTICAST_MASK(port) (RTL8370_PORT0_UNKNOWN_IP4_MCAST_MASK << RTL8370_UNKNOWN_L2_MULTICAST_OFFSET(port))
|
||||
|
||||
#define RTL8370_PORT_TRUNK_CTRL_REG RTL8370_REG_PORT_TRUNK_CTRL
|
||||
#define RTL8370_PORT_TRUNK_HASH_MASK 0x007F
|
||||
|
||||
#define RTL8370_PORT_TRUNK_GROUP_MASK_REG RTL8370_REG_PORT_TRUNK_GROUP_MASK
|
||||
#define RTL8370_PORT_TRUNK_GROUP_MASK_OFFSET(group) (group << 2)
|
||||
#define RTL8370_PORT_TRUNK_GROUP_MASK_MASK(group) (RTL8370_PORT_TRUNK_GROUP0_MASK_MASK << RTL8370_PORT_TRUNK_GROUP_MASK_OFFSET(group))
|
||||
|
||||
#define RTL8370_PORT_TRUNK_FLOWCTRL_REG RTL8370_REG_PORT_TRUNK_FLOWCTRL
|
||||
|
||||
#define RTL8370_QOS_PORT_QUEUE_NUMBER_BASE RTL8370_REG_QOS_PORT_QUEUE_NUMBER_CTRL0
|
||||
#define RTL8370_QOS_PORT_QUEUE_NUMBER_REG(port) (RTL8370_QOS_PORT_QUEUE_NUMBER_BASE + (port >> 2))
|
||||
#define RTL8370_QOS_PORT_QUEUE_NUMBER_OFFSET(port) ((port & 0x3) << 2)
|
||||
#define RTL8370_QOS_PORT_QUEUE_NUMBER_MASK(port) (0x7 << RTL8370_QOS_PORT_QUEUE_NUMBER_OFFSET(port))
|
||||
|
||||
#define RTL8370_QOS_1Q_PRIORITY_TO_QID_BASE RTL8370_REG_QOS_1Q_PRIORITY_TO_QID_CRTL0
|
||||
#define RTL8370_QOS_1Q_PRIORITY_TO_QID_REG(index, pri) (RTL8370_QOS_1Q_PRIORITY_TO_QID_BASE + (index << 1) + (pri >> 2))
|
||||
#define RTL8370_QOS_1Q_PRIORITY_TO_QID_OFFSET(pri) ((pri & 0x3) << 2)
|
||||
#define RTL8370_QOS_1Q_PRIORITY_TO_QID_MASK(pri) (RTL8370_QOS_1Q_PRIORITY_TO_QID_CRTL0_PRIORITY0_TO_QID_MASK << RTL8370_QOS_1Q_PRIORITY_TO_QID_OFFSET(pri))
|
||||
|
||||
#define RTL8370_DEBUG_INFO_BASE RTL8370_REG_PORT_DEBUG_INFO_CTRL0
|
||||
#define RTL8370_DEBUG_INFO_REG(port) (RTL8370_DEBUG_INFO_BASE + (port >>1))
|
||||
#define RTL8370_DEBUG_INFO_OFFSET(port) ((port&1)<<3)
|
||||
#define RTL8370_DEBUG_INFO_MASK(port) (RTL8370_PORT0_DEBUG_INFO_MASK << RTL8370_DEBUG_INFO_OFFSET(port))
|
||||
|
||||
/* (16'h0a00) l2_reg */
|
||||
|
||||
#define RTL8370_VLAN_MSTI_BASE RTL8370_REG_VLAN_MSTI0_CTRL0
|
||||
#define RTL8370_VLAN_MSTI_REG(tree, port) (RTL8370_VLAN_MSTI_BASE + (tree << 1) + (port >> 3))
|
||||
#define RTL8370_VLAN_MSTI_OFFSET(port) ((port & 0x7) << 1)
|
||||
#define RTL8370_VLAN_MSTI_MASK(port) (RTL8370_VLAN_MSTI0_CTRL0_PORT0_STATE_MASK << RTL8370_VLAN_MSTI_OFFSET(port))
|
||||
|
||||
#define RTL8370_LUT_PORT_LEARN_LIMITNO_BASE RTL8370_REG_LUT_PORT0_LEARN_LIMITNO
|
||||
#define RTL8370_LUT_PORT_LEARN_LIMITNO_REG(port) (RTL8370_LUT_PORT_LEARN_LIMITNO_BASE + port)
|
||||
#define RTL8370_LUT_PORT_LEARN_LIMITNO_OFFSET RTL8370_LUT_PORT0_LEARN_LIMITNO_OFFSET
|
||||
#define RTL8370_LUT_PORT_LEARN_LIMITNO_MASK RTL8370_LUT_PORT0_LEARN_LIMITNO_MASK
|
||||
|
||||
#define RTL8370_LUT_CFG_REG RTL8370_REG_LUT_CFG
|
||||
|
||||
#define RTL8370_LUT_AGEOUT_CRTL_REG RTL8370_REG_LUT_AGEOUT_CRTL
|
||||
|
||||
#define RTL8370_FORCE_FLUSH_REG RTL8370_REG_FORCE_FLUSH
|
||||
|
||||
#define RTL8370_STORM_BCAST_REG RTL8370_REG_STORM_BCAST
|
||||
|
||||
#define RTL8370_STORM_MCAST_REG RTL8370_REG_STORM_MCAST
|
||||
|
||||
#define RTL8370_STORM_UNKNOWN_UCAST_REG RTL8370_REG_STORM_UNKOWN_UCAST
|
||||
|
||||
#define RTL8370_STORM_UNKNOWN_MCAST_REG RTL8370_REG_STORM_UNKOWN_MCAST
|
||||
|
||||
#define RTL8370_STORM_BCAST_METER_CRTL_BASE RTL8370_REG_STORM_BCAST_METER_CRTL0
|
||||
#define RTL8370_STORM_BCAST_METER_CRTL_REG(port) (RTL8370_STORM_BCAST_METER_CRTL_BASE + (port >> 1))
|
||||
#define RTL8370_STORM_BCAST_METER_CRTL_OFFSET(port) ((port & 0x1) << 3)
|
||||
#define RTL8370_STORM_BCAST_METER_CRTL_MASK(port) (0xFF << RTL8370_STORM_BCAST_METER_CRTL_OFFSET(port))
|
||||
|
||||
#define RTL8370_STORM_MCAST_METER_CRTL_BASE RTL8370_REG_STORM_MCAST_METER_CRTL0
|
||||
#define RTL8370_STORM_MCAST_METER_CRTL_REG(port) (RTL8370_STORM_MCAST_METER_CRTL_BASE + (port >> 1))
|
||||
#define RTL8370_STORM_MCAST_METER_CRTL_OFFSET(port) ((port & 0x1) << 3)
|
||||
#define RTL8370_STORM_MCAST_METER_CRTL_MASK(port) (0xFF << RTL8370_STORM_MCAST_METER_CRTL_OFFSET(port))
|
||||
|
||||
#define RTL8370_STORM_UNDA_METER_CRTL_BASE RTL8370_REG_STORM_UNDA_METER_CRTL0
|
||||
#define RTL8370_STORM_UNDA_METER_CRTL_REG(port) (RTL8370_STORM_UNDA_METER_CRTL_BASE + (port >> 1))
|
||||
#define RTL8370_STORM_UNDA_METER_CRTL_OFFSET(port) ((port & 0x1) << 3)
|
||||
#define RTL8370_STORM_UNDA_METER_CRTL_MASK(port) (0xFF << RTL8370_STORM_UNDA_METER_CRTL_OFFSET(port))
|
||||
|
||||
#define RTL8370_STORM_UNMC_METER_CRTL_BASE RTL8370_REG_STORM_UNMC_METER_CRTL0
|
||||
#define RTL8370_STORM_UNMC_METER_CRTL_REG(port) (RTL8370_STORM_UNMC_METER_CRTL_BASE + (port >> 1))
|
||||
#define RTL8370_STORM_UNMC_METER_CRTL_OFFSET(port) ((port & 0x1) << 3)
|
||||
#define RTL8370_STORM_UNMC_METER_CRTL_MASK(port) (0xFF << RTL8370_STORM_UNMC_METER_CRTL_OFFSET(port))
|
||||
|
||||
#define RTL8370_OAM_PARSER_BASE RTL8370_REG_OAM_PARSER_CTRL0
|
||||
#define RTL8370_OAM_PARSER_REG(port) (RTL8370_OAM_PARSER_BASE + (port >> 3))
|
||||
#define RTL8370_OAM_PARSER_OFFSET(port) ((port & 0x7) *2)
|
||||
#define RTL8370_OAM_PARSER_MASK(port) (RTL8370_PORT0_PARACT_MASK << RTL8370_OAM_PARSER_OFFSET(port))
|
||||
|
||||
#define RTL8370_OAM_MULTIPLEXER_BASE RTL8370_REG_OAM_MULTIPLEXER_CTRL0
|
||||
#define RTL8370_OAM_MULTIPLEXER_REG(port) (RTL8370_OAM_MULTIPLEXER_BASE + (port >> 3))
|
||||
#define RTL8370_OAM_MULTIPLEXER_OFFSET(port) ((port & 0x7) * 2)
|
||||
#define RTL8370_OAM_MULTIPLEXER_MASK(port) (RTL8370_PORT0_PARACT_MASK << RTL8370_OAM_MULTIPLEXER_OFFSET(port))
|
||||
|
||||
#define RTL8370_OAM_CTRL_REG RTL8370_REG_OAM_CTRL
|
||||
|
||||
#define RTL8370_DOT1X_PORT_ENABLE_REG RTL8370_REG_DOT1X_PORT_ENABLE
|
||||
|
||||
#define RTL8370_DOT1X_MAC_ENABLE_REG RTL8370_REG_DOT1X_MAC_ENABLE
|
||||
|
||||
#define RTL8370_DOT1X_PORT_AUTH_REG RTL8370_REG_DOT1X_PORT_AUTH
|
||||
|
||||
#define RTL8370_DOT1X_PORT_OPDIR_REG RTL8370_REG_DOT1X_PORT_OPDIR
|
||||
|
||||
#define RTL8370_DOT1X_UNAUTH_ACT_BASE RTL8370_REG_DOT1X_UNAUTH_ACT_W0
|
||||
#define RTL8370_DOT1X_UNAUTH_ACT_REG(port) (RTL8370_DOT1X_UNAUTH_ACT_BASE + (port >> 3))
|
||||
#define RTL8370_DOT1X_UNAUTH_ACT_OFFSET(port) ((port & 0x7) << 1)
|
||||
#define RTL8370_DOT1X_UNAUTH_ACT_MASK(port) (RTL8370_DOT1X_PORT0_UNAUTHBH_MASK << RTL8370_DOT1X_UNAUTH_ACT_OFFSET(port))
|
||||
|
||||
#define RTL8370_DOT1X_CFG_REG RTL8370_REG_DOT1X_CFG
|
||||
|
||||
#define RTL8370_REG_L2_LRN_CNT_BASE RTL8370_REG_L2_LRN_CNT_CTRL0
|
||||
#define RTL8370_REG_L2_LRN_CNT_REG(port) (RTL8370_REG_L2_LRN_CNT_BASE + port)
|
||||
|
||||
/* (16'h0b00) mltvlan_reg */
|
||||
|
||||
#define RTL8370SG_SVLAN_MCAST2S_ENTRY_BASE_REG RTL8370_REG_SVLAN_MCAST2S_ENTRY0_CTRL0
|
||||
|
||||
/* (16'h0c00) svlan_reg */
|
||||
|
||||
#define RTL8370_SVLAN_MEMBERCFG_BASE_REG RTL8370_REG_SVLAN_MEMBERCFG0_CTRL0
|
||||
#define RTL8370SG_SVLAN_C2SCFG_BASE_REG RTL8370_REG_SVLAN_C2SCFG0_CTRL0
|
||||
#define RTL8370_SVLAN_CFG_REG RTL8370_REG_SVLAN_CFG
|
||||
|
||||
/* (16'h0f00) hsactrl_reg */
|
||||
|
||||
#define RTL8370_SVLAN_S2C_ENTRY_BASE_REG RTL8370_REG_SVLAN_SP2C_ENTRY0_CTRL0
|
||||
|
||||
/* (16'h1000) mib_reg */
|
||||
|
||||
#define RTL8370_MIB_COUNTER_BASE_REG RTL8370_REG_MIB_COUNTER0
|
||||
|
||||
#define RTL8370_MIB_ADDRESS_REG RTL8370_REG_MIB_ADDRESS
|
||||
|
||||
#define RTL8370_MIB_CTRL_REG RTL8370_REG_MIB_CTRL0
|
||||
#define RTL8370_MIB_PORT07_MASK (0xFF<<RTL8370_PORT0_RESET_OFFSET)
|
||||
#define RTL8370_MIB_PORT815_MASK (0xFF<<RTL8370_PORT8_RESET_OFFSET)
|
||||
|
||||
/* (16'h1100) intrpt_reg */
|
||||
|
||||
#define RTL8370_INTR_CTRL_REG RTL8370_REG_INTR_CTRL
|
||||
|
||||
#define RTL8370_INTR_IMR_REG RTL8370_REG_INTR_IMR
|
||||
|
||||
#define RTL8370_INTR_IMS_REG RTL8370_REG_INTR_IMS
|
||||
|
||||
#define RTL8370_INTR_INDICATOR_BASED RTL8370_REG_LEARN_OVER_INDICATOR
|
||||
#define RTL8370_LEARN_OVER_INDICATOR_REG RTL8370_REG_LEARN_OVER_INDICATOR
|
||||
|
||||
#define RTL8370_SPEED_CHANGE_INDICATOR_REG RTL8370_REG_SPEED_CHANGE_INDICATOR
|
||||
|
||||
#define RTL8370_PORT_LINKDOWN_INDICATOR_REG RTL8370_REG_PORT_LINKDOWN_INDICATOR
|
||||
|
||||
#define RTL8370_PORT_LINKUP_INDICATOR_REG RTL8370_REG_PORT_LINKUP_INDICATOR
|
||||
|
||||
#define RTL8370_REG_METER_EXCEED_INDICATOR_BASE RTL8370_REG_METER_EXCEED_INDICATOR0
|
||||
#define RTL8370_REG_METER_EXCEED_INDICATOR_REG(meter) (RTL8370_REG_METER_EXCEED_INDICATOR_BASE + (meter >> 4))
|
||||
#define RTL8370_REG_METER_EXCEED_INDICATOR_OFFSET(meter) (meter & 0xF)
|
||||
#define RTL8370_REG_METER_EXCEED_INDICATOR_MASK(meter) (RTL8370_METER0_MASK << RTL8370_REG_METER_EXCEED_INDICATOR_OFFSET(meter))
|
||||
|
||||
/* (16'h1200) swcore_reg */
|
||||
|
||||
#define RTL8370_VS_TPID_REG RTL8370_REG_VS_TPID
|
||||
|
||||
#define RTL8370_SWITCH_MAC_BASE RTL8370_REG_SWITCH_MAC2
|
||||
|
||||
#define RTL8370_REMARKING_CTRL_REG RTL8370_REG_SWITCH_CTRL0
|
||||
|
||||
#define RTL8370_QOS_DSCP_REMARK_BASE RTL8370_REG_QOS_DSCP_REMARK_CTRL0
|
||||
#define RTL8370_QOS_DSCP_REMARK_REG(pri) (RTL8370_QOS_DSCP_REMARK_BASE + (pri >> 1))
|
||||
#define RTL8370_QOS_DSCP_REMARK_OFFSET(pri) (((pri) & 0x1) << 3)
|
||||
#define RTL8370_QOS_DSCP_REMARK_MASK(pri) (0x3F << RTL8370_QOS_DSCP_REMARK_OFFSET(pri))
|
||||
|
||||
#define RTL8370_QOS_1Q_REMARK_BASE RTL8370_REG_QOS_1Q_REMARK_CTRL0
|
||||
#define RTL8370_QOS_1Q_REMARK_REG(pri) (RTL8370_QOS_1Q_REMARK_BASE + (pri >> 2))
|
||||
#define RTL8370_QOS_1Q_REMARK_OFFSET(pri) ((pri & 0x3) << 2)
|
||||
#define RTL8370_QOS_1Q_REMARK_MASK(pri) (0x7 << RTL8370_QOS_1Q_REMARK_OFFSET(pri))
|
||||
|
||||
#define RTL8370_PTKGEN_PAYLOAD_CTRL0_REG RTL8370_REG_PTKGEN_PAYLOAD_CTRL0
|
||||
|
||||
#define RTL8370_PTKGEN_PAYLOAD_CTRL1_REG RTL8370_REG_PTKGEN_PAYLOAD_CTRL1
|
||||
|
||||
#define RTL8370_PTKGEN_PAUSE_TIME_REG RTL8370_REG_PTKGEN_PAUSE_TIME
|
||||
|
||||
#define RTL8370_TX_STOP_REG RTL8370_REG_TX_STOP
|
||||
|
||||
#define RTL8370_SVLAN_UPLINK_PORTMASK_REG RTL8370_REG_SVLAN_UPLINK_PORTMASK
|
||||
|
||||
#define RTL8370_CPU_PORT_MASK_REG RTL8370_REG_CPU_PORT_MASK
|
||||
|
||||
#define RTL8370_CPU_CTRL_REG RTL8370_REG_CPU_CTRL
|
||||
|
||||
#define RTL8370_MIRROR_CTRL_REG RTL8370_REG_MIRROR_CTRL
|
||||
|
||||
#define RTL8370_FLOWCTRL_CTRL_REG RTL8370_REG_FLOWCTRL_CTRL0
|
||||
|
||||
#define RTL8370_FLOWCTRL_ALL_ON_REG RTL8370_REG_FLOWCTRL_ALL_ON
|
||||
|
||||
#define RTL8370_FLOWCTRL_SYS_ON_REG RTL8370_REG_FLOWCTRL_SYS_ON
|
||||
|
||||
#define RTL8370_FLOWCTRL_SYS_OFF_REG RTL8370_REG_FLOWCTRL_SYS_OFF
|
||||
|
||||
#define RTL8370_FLOWCTRL_SHARE_ON_REG RTL8370_REG_FLOWCTRL_SHARE_ON
|
||||
|
||||
#define RTL8370_FLOWCTRL_SHARE_OFF_REG RTL8370_REG_FLOWCTRL_SHARE_OFF
|
||||
|
||||
#define RTL8370_FLOWCTRL_FCOFF_SYS_ON_REG RTL8370_REG_FLOWCTRL_FCOFF_SYS_ON
|
||||
|
||||
#define RTL8370_FLOWCTRL_FCOFF_SYS_OFF_REG RTL8370_REG_FLOWCTRL_FCOFF_SYS_OFF
|
||||
|
||||
#define RTL8370_FLOWCTRL_FCOFF_SHARE_ON_REG RTL8370_REG_FLOWCTRL_FCOFF_SHARE_ON
|
||||
|
||||
#define RTL8370_FLOWCTRL_FCOFF_SHARE_OFF_REG RTL8370_REG_FLOWCTRL_FCOFF_SHARE_OFF
|
||||
|
||||
#define RTL8370_FLOWCTRL_PORT_ON_REG RTL8370_REG_FLOWCTRL_PORT_ON
|
||||
|
||||
#define RTL8370_FLOWCTRL_PORT_OFF_REG RTL8370_REG_FLOWCTRL_PORT_OFF
|
||||
|
||||
#define RTL8370_FLOWCTRL_PORT_PRIVATE_ON_REG RTL8370_REG_FLOWCTRL_PORT_PRIVATE_ON
|
||||
|
||||
#define RTL8370_FLOWCTRL_PORT_PRIVATE_OFF_REG RTL8370_REG_FLOWCTRL_PORT_PRIVATE_OFF
|
||||
|
||||
#define RTL8370_RRCP_CTRL0_REG RTL8370_REG_RRCP_CTRL0
|
||||
|
||||
#define RTL8370_RRCP_PRIVATE_KEY_REG RTL8370_REG_RRCP_CTRL1
|
||||
|
||||
#define RTL8370_RRCP_AUTH_KEY_REG RTL8370_REG_RRCP_CTRL2
|
||||
|
||||
#define RTL8370_RRCP_TRUST_PORTMASK_REG RTL8370_REG_RRCP_CTRL3
|
||||
|
||||
#define RTL8370_FLOWCTRL_FCOFF_PORT_ON_REG RTL8370_REG_FLOWCTRL_FCOFF_PORT_ON
|
||||
|
||||
#define RTL8370_FLOWCTRL_FCOFF_PORT_OFF_REG RTL8370_REG_FLOWCTRL_FCOFF_PORT_OFF
|
||||
|
||||
#define RTL8370_FLOWCTRL_FCOFF_PORT_PRIVATE_ON_REG RTL8370_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_ON
|
||||
|
||||
#define RTL8370_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF_REG RTL8370_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF
|
||||
|
||||
#define RTL8370_FLOWCRTL_EGRESS_QUEUE_ENABLE_BASE RTL8370_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL0
|
||||
#define RTL8370_FLOWCRTL_EGRESS_QUEUE_ENABLE_REG(port) (RTL8370_FLOWCRTL_EGRESS_QUEUE_ENABLE_BASE + (port >> 1))
|
||||
#define RTL8370_FLOWCRTL_EGRESS_QUEUE_ENABLE_REG_OFFSET(port) ((port & 0x1) << 3)
|
||||
#define RTL8370_FLOWCRTL_EGRESS_QUEUE_ENABLE_REG_MASK(port) (RTL8370_PORT0_QUEUE_MASK_MASK << RTL8370_FLOWCRTL_EGRESS_QUEUE_ENABLE_REG_OFFSET(port))
|
||||
|
||||
#define RTL8370_FLOWCRTL_EGRESS_PORT_ENABLE_REG RTL8370_REG_FLOWCRTL_EGRESS_PORT_ENABLE
|
||||
|
||||
#define RTL8370_FLOWCTRL_TOTAL_PAGE_COUNTER_REG RTL8370_REG_FLOWCTRL_TOTAL_PAGE_COUNTER
|
||||
|
||||
#define RTL8370_FLOWCTRL_PUBLIC_PAGE_COUNTER_REG RTL8370_REG_FLOWCTRL_PUBLIC_PAGE_COUNTER
|
||||
|
||||
#define RTL8370_FLOWCTRL_TOTAL_PAGE_MAX_REG RTL8370_REG_FLOWCTRL_TOTAL_PAGE_MAX
|
||||
|
||||
#define RTL8370_FLOWCTRL_PUBLIC_PAGE_MAX_REG RTL8370_REG_FLOWCTRL_PUBLIC_PAGE_MAX
|
||||
|
||||
#define RTL8370_FLOWCTRL_PORT_PAGE_COUNTER_BASE RTL8370_REG_FLOWCTRL_PORT0_PAGE_COUNTER
|
||||
#define RTL8370_FLOWCTRL_PORT_PAGE_COUNTER_REG(port) (RTL8370_FLOWCTRL_PORT_PAGE_COUNTER_BASE + port)
|
||||
#define RTL8370_FLOWCTRL_PORT_PAGE_COUNTER_MASK RTL8370_FLOWCTRL_PORT0_PAGE_COUNTER_MASK
|
||||
|
||||
#define RTL8370_FLOWCTRL_PORT_PAGE_MAX_BASE RTL8370_REG_FLOWCTRL_PORT0_PAGE_MAX
|
||||
#define RTL8370_FLOWCTRL_PORT_PAGE_MAX_REG(port) (RTL8370_FLOWCTRL_PORT_PAGE_MAX_BASE + port)
|
||||
#define RTL8370_FLOWCTRL_PORT_PAGE_MAX_MASK RTL8370_FLOWCTRL_PORT0_PAGE_MAX_MASK
|
||||
|
||||
/* (16'h1300) chip_reg*/
|
||||
|
||||
/* (16'h1400) mtrpool_reg */
|
||||
#define RTL8370_METER_RATE_BASE RTL8370_REG_METER0_RATE_CTRL0
|
||||
#define RTL8370_METER_RATE_REG(meter) ((meter << 1) + RTL8370_METER_RATE_BASE)
|
||||
|
||||
#define RTL8370_METER_BUCKET_SIZE_BASE RTL8370_REG_METER0_BUCKET_SIZE
|
||||
#define RTL8370_METER_BUCKET_SIZE_REG(meter) (RTL8370_METER_BUCKET_SIZE_BASE + meter)
|
||||
|
||||
#define RTL8370_LEAKY_BUCKET_TICK_REG RTL8370_REG_METER_CTRL0
|
||||
#define RTL8370_LEAKY_BUCKET_TICK_OFFSET 0
|
||||
#define RTL8370_LEAKY_BUCKET_TICK_MASK 0xFF
|
||||
|
||||
#define RTL8370_LEAKY_BUCKET_TOKEN_REG RTL8370_REG_METER_CTRL1
|
||||
#define RTL8370_LEAKY_BUCKET_TOKEN_OFFSET 0
|
||||
#define RTL8370_LEAKY_BUCKET_TOKEN_MASK 0xFF
|
||||
|
||||
#define RTL8370_METER_OVERRATE_INDICATOR_BASE RTL8370_REG_METER_OVERRATE_INDICATOR0
|
||||
#define RTL8370_METER_OVERRATE_INDICATOR_REG(meter) (RTL8370_METER_OVERRATE_INDICATOR_BASE + (meter >> 4))
|
||||
#define RTL8370_METER_EXCEED_OFFSET(meter) (meter & 0xF)
|
||||
#define RTL8370_METER_EXCEED_MASK(meter) (1 << RTL8370_METER_EXCEED_OFFSET(meter))
|
||||
|
||||
#define RTL8370_METER_IFG_CTRL_BASE RTL8370_REG_METER_IFG_CTRL0
|
||||
#define RTL8370_METER_IFG_CTRL_REG(meter) (RTL8370_METER_IFG_CTRL_BASE + (meter >> 4))
|
||||
#define RTL8370_METER_IFG_OFFSET(meter) (meter & 0xF)
|
||||
#define RTL8370_METER_IFG_MASK(meter) (1 << RTL8370_METER_IFG_OFFSET(meter))
|
||||
|
||||
#define RTL8370_FLOWCTRL_CTRL_REG RTL8370_REG_FLOWCTRL_CTRL0
|
||||
|
||||
/* (16'h1800)8051_RLDP_EEE_reg */
|
||||
|
||||
#define RTL8370_DW8051_IMR_REG RTL8370_REG_DW8051_IMR
|
||||
|
||||
#define RTL8370_DW8051_IMS_REG RTL8370_REG_DW8051_IMS
|
||||
|
||||
#define RTL8370_DW8051_PROP_REG_BASE RTL8370_REG_DW8051_CTRL0
|
||||
|
||||
#define RTL8370_EEELLDP_CTRL0_REG RTL8370_REG_EEELLDP_CTRL0
|
||||
|
||||
#define RTL8370_EEELLDP_CTRL1_REG RTL8370_REG_EEELLDP_CTRL1
|
||||
|
||||
#define RTL8370_EEELLDP_PMSK_REG RTL8370_REG_EEELLDP_PMSK
|
||||
|
||||
#define RTL8370_EEELLDP_TX_FRAMEU_REG_BASE RTL8370_REG_EEELLDP_FRAMEU00
|
||||
|
||||
#define RTL8370_EEELLDP_TX_CAP_FRAMEL_REG_BASE RTL8370_REG_EEELLDP_CAP_FRAMEL00
|
||||
|
||||
#define RTL8370_EEELLDP_TX_ACK_FRAMEL_REG_BASE RTL8370_REG_EEELLDP_ACK_FRAMEL00
|
||||
|
||||
#define RTL8370_EEELLDP_RX_VALUE_PORT_BASE RTL8370_REG_EEELLDP_RX_VALUE_P00_00
|
||||
#define RTL8370_EEELLDP_RX_VALUE_PORT_REG(port) (RTL8370_EEELLDP_RX_VALUE_PORT_BASE + (port * 9))
|
||||
|
||||
#define RTL8370_RLDP_CTRL0_REG RTL8370_REG_RLDP_CTRL0
|
||||
|
||||
/* data writen to [15:8] will be writen to writen to [7:0] */
|
||||
/* However, the read operation is normal */
|
||||
#define RTL8370_RLDP_RETRY_COUNT_LOOPSTATE_READ_OFFSET 0
|
||||
#define RTL8370_RLDP_RETRY_COUNT_LOOPSTATE_READ_MASK 0xFF
|
||||
#define RTL8370_RLDP_RETRY_COUNT_CHKSTATE_READ_OFFSET 8
|
||||
#define RTL8370_RLDP_RETRY_COUNT_CHKSTATE_READ_MASK 0xFF00
|
||||
#define RTL8370_RLDP_RETRY_COUNT_LOOPSTATE_WRITE_OFFSET 0
|
||||
#define RTL8370_RLDP_RETRY_COUNT_LOOPSTATE_WRITE_MASK 0xFF
|
||||
#define RTL8370_RLDP_RETRY_COUNT_CHKSTATE_WRITE_OFFSET 8
|
||||
#define RTL8370_RLDP_RETRY_COUNT_CHKSTATE_WRITE_MASK 0xFF00
|
||||
|
||||
#define RTL8370_RLDP_RETRY_COUNT_REG RTL8370_REG_RLDP_CTRL1
|
||||
|
||||
#define RTL8370_RLDP_RETRY_PERIOD_LOOPSTATE_REG RTL8370_REG_RLDP_CTRL2
|
||||
|
||||
#define RTL8370_RLDP_RETRY_PERIOD_CHKSTATE_REG RTL8370_REG_RLDP_CTRL3
|
||||
|
||||
#define RTL8370_RLDP_TX_PMSK_REG RTL8370_REG_RLDP_CTRL4
|
||||
|
||||
#define RTL8370_RLDP_RAND_NUM_REG_BASE RTL8370_REG_RLDP_RAND_NUM0
|
||||
|
||||
#define RTL8370_RLDP_SEED_NUM_REG_BASE RTL8370_REG_RLDP_SEED_NUM2
|
||||
|
||||
#define RTL8370_RLDP_LOOP_PMSK_REG RTL8370_REG_RLDP_LOOP_PMSK
|
||||
|
||||
#define RTL8370_RLDP_LOOP_PORT_BASE RTL8370_REG_RLDP_LOOP_PORT_REG0
|
||||
#define RTL8370_RLDP_LOOP_PORT_REG(port) (RTL8370_RLDP_LOOP_PORT_BASE + (port >> 1))
|
||||
#define RTL8370_RLDP_LOOP_PORT_OFFSET(port) ((port & 0x1) << 3)
|
||||
#define RTL8370_RLDP_LOOP_PORT_MASK(port) (RTL8370_RLDP_LOOP_PORT_00_MASK << RTL8370_RLDP_LOOP_PORT_OFFSET(port))
|
||||
|
||||
#define RTL8370_PAGEMETER_PORT_BASE RTL8370_REG_PAGEMETER_PORT0_CTRL0
|
||||
#define RTL8370_PAGEMETER_PORT_REG(port) (RTL8370_PAGEMETER_PORT_BASE + 0x20*port)
|
||||
|
||||
#define RTL8370_HIGHPRI_INDICATOR_REG RTL8370_REG_HIGHPRI_INDICATOR
|
||||
#define RTL8370_PORT_INDICATOR_OFFSET(port) (port)
|
||||
#define RTL8370_PORT_INDICATOR_MASK(port) (RTL8370_PORT0_INDICATOR_MASK << RTL8370_PORT_INDICATOR_OFFSET(port))
|
||||
|
||||
#define RTL8370_HIGHPRI_CFG_REG RTL8370_REG_HIGHPRI_CFG
|
||||
|
||||
#define RTL8370_PKG_CFG_BASE RTL8370_REG_PKTGEN_PORT0_CTRL
|
||||
#define RTL8370_PKG_CFG_REG(port) (RTL8370_PKG_CFG_BASE + (port*0x20))
|
||||
|
||||
#define RTL8370_PKG_DA_BASE RTL8370_REG_PKTGEN_PORT0_DA0
|
||||
#define RTL8370_PKG_DA_REG(port) (RTL8370_PKG_DA_BASE + (port*0x20))
|
||||
|
||||
#define RTL8370_PKG_SA_BASE RTL8370_REG_PKTGEN_PORT0_SA0
|
||||
#define RTL8370_PKG_SA_REG(port) (RTL8370_PKG_SA_BASE + (port*0x20))
|
||||
|
||||
#define RTL8370_PKG_NUM_BASE RTL8370_REG_PKTGEN_PORT0_COUNTER0
|
||||
#define RTL8370_PKG_NUM_REG(port) (RTL8370_PKG_NUM_BASE + (port*0x20))
|
||||
|
||||
#define RTL8370_PKG_LENGTH_BASE RTL8370_REG_PKTGEN_PORT0_TX_LENGTH
|
||||
#define RTL8370_PKG_LENGTH_REG(port) (RTL8370_PKG_LENGTH_BASE + (port*0x20))
|
||||
|
||||
#define RTL8370_PKG_MAXLENTH_BASE RTL8370_REG_PKTGEN_PORT0_MAX_LENGTH
|
||||
#define RTL8370_PKG_MAXLENGTH_REG(port) (RTL8370_PKG_MAXLENTH_BASE + (port*0x20))
|
||||
|
||||
|
||||
#define RTL8370_ALDP_CFG_REG RTL8370_REG_UPS_CTRL2
|
||||
#define RTL8370_ALDP_ENABLE_OFFSET 14
|
||||
|
||||
#endif /*#ifndef _RTL8370_BASE_H_*/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,12 @@
|
|||
|
||||
#ifndef __SMI_H__
|
||||
#define __SMI_H__
|
||||
|
||||
#include "rtk_error.h"
|
||||
#include "rtk_types.h"
|
||||
|
||||
int smi_init(uint8 pinSCK, uint8 pinSDA, uint8 switchAddr);
|
||||
int smi_read(uint16 reg, uint16 *data);
|
||||
int smi_write(uint16 reg, uint16 data);
|
||||
|
||||
#endif /* __SMI_H__ */
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
#include "rtk_error.h"
|
||||
#include "rtk_types.h"
|
||||
|
||||
void switch_hard_reset(int newState);
|
||||
|
||||
rtk_api_ret_t switch_init();
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
; PlatformIO Project Configuration File
|
||||
;
|
||||
; Build options: build flags, source filter
|
||||
; Upload options: custom upload port, speed and extra flags
|
||||
; Library options: dependencies, extra library storages
|
||||
; Advanced options: extra scripting
|
||||
;
|
||||
; Please visit documentation for the other options and examples
|
||||
; https://docs.platformio.org/page/projectconf.html
|
||||
|
||||
|
||||
[env:smart_switch]
|
||||
platform = espressif32
|
||||
board = sistematics_smart_switch
|
||||
framework = arduino
|
||||
monitor_speed = 9600
|
||||
build_flags = -I include/rtl8370
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
#include <Arduino.h>
|
||||
#include "board.h"
|
||||
#include "switch.h"
|
||||
|
||||
void setup()
|
||||
{
|
||||
rtk_api_ret_t error;
|
||||
|
||||
pinMode(BLUE_LED, OUTPUT);
|
||||
pinMode(SWITCH_RESET, OUTPUT);
|
||||
digitalWrite(BLUE_LED, HIGH);
|
||||
|
||||
Serial.begin(9600);
|
||||
while (!Serial)
|
||||
delay(10);
|
||||
|
||||
error = switch_init();
|
||||
|
||||
if (error)
|
||||
{
|
||||
Serial.printf("Error initializing RTL8370 device: %d\n", error);
|
||||
}
|
||||
}
|
||||
|
||||
void loop()
|
||||
{
|
||||
/*byte error, address;
|
||||
int nDevices;
|
||||
|
||||
Serial.println("Scanning...");
|
||||
|
||||
nDevices = 0;
|
||||
for (address = 1; address < 127; address++)
|
||||
{
|
||||
// The i2c_scanner uses the return value of
|
||||
// the Write.endTransmisstion to see if
|
||||
// a device did acknowledge to the address.
|
||||
Wire.beginTransmission(address);
|
||||
error = Wire.endTransmission();
|
||||
|
||||
if (error == 0)
|
||||
{
|
||||
Serial.print("I2C device found at address 0x");
|
||||
if (address < 16)
|
||||
Serial.print("0");
|
||||
Serial.print(address, HEX);
|
||||
Serial.println(" !");
|
||||
|
||||
nDevices++;
|
||||
}
|
||||
else if (error == 4)
|
||||
{
|
||||
Serial.print("Unknown error at address 0x");
|
||||
if (address < 16)
|
||||
Serial.print("0");
|
||||
Serial.println(address, HEX);
|
||||
}
|
||||
}
|
||||
if (nDevices == 0)
|
||||
Serial.println("No I2C devices found\n");
|
||||
else
|
||||
Serial.println("done\n");
|
||||
|
||||
delay(5000); // wait 5 seconds for next scan
|
||||
*/
|
||||
}
|
||||
|
|
@ -0,0 +1,153 @@
|
|||
#include <rtl8370_asicdrv.h>
|
||||
#include <rtl8370_asicdrv_phy.h>
|
||||
#include <rtk_api.h>
|
||||
|
||||
#include <rtk_api_ext.h>
|
||||
#include <rtk_error.h>
|
||||
|
||||
#include <string.h>
|
||||
|
||||
/* Function Name:
|
||||
* rtk_switch_init
|
||||
* Description:
|
||||
* Set chip to default configuration enviroment
|
||||
* Input:
|
||||
* None
|
||||
* Output:
|
||||
* None
|
||||
* Return:
|
||||
* RT_ERR_OK - OK
|
||||
* RT_ERR_FAILED - FAILED
|
||||
* RT_ERR_SMI - SMI access error
|
||||
* Note:
|
||||
* The API can set chip registers to default configuration for different release chip model.
|
||||
*/
|
||||
rtk_api_ret_t rtk_switch_init(void)
|
||||
{
|
||||
rtk_api_ret_t retVal;
|
||||
uint16 regData1, regData2;
|
||||
|
||||
if ((retVal = rtl8370_setAsicReg(RTL8370_REG_MAGIC_ID, 0x0249)) != RT_ERR_OK)
|
||||
return retVal;
|
||||
|
||||
if ((retVal = rtl8370_getAsicRegBits(RTL8370_REG_CHIP_VER, 0xF000, ®Data1)) != RT_ERR_OK)
|
||||
return retVal;
|
||||
|
||||
if ((retVal = rtl8370_setAsicPHYReg(0, 31, 5)) != RT_ERR_OK)
|
||||
return retVal;
|
||||
if ((retVal = rtl8370_setAsicPHYReg(0, 5, 0x3ffe)) != RT_ERR_OK)
|
||||
return retVal;
|
||||
if ((retVal = rtl8370_getAsicPHYReg(0, 6, ®Data2)) != RT_ERR_OK)
|
||||
return retVal;
|
||||
|
||||
printf("regData1: %x\nregData: %x", regData1, regData2);
|
||||
|
||||
/*if (0 == regData1)
|
||||
{
|
||||
if ((retVal = _rtk_switch_init0()) != RT_ERR_OK)
|
||||
return retVal;
|
||||
}
|
||||
else if (1 == regData1)
|
||||
{
|
||||
if (0x94eb == regData2)
|
||||
{
|
||||
if ((retVal = _rtk_switch_init1()) != RT_ERR_OK)
|
||||
return retVal;
|
||||
}
|
||||
else if (0x2104 == regData2)
|
||||
{
|
||||
if ((retVal = _rtk_switch_init2()) != RT_ERR_OK)
|
||||
return retVal;
|
||||
}
|
||||
}*/
|
||||
|
||||
/*Enable System Based LED*/
|
||||
if ((retVal = rtl8370_setAsicRegBit(RTL8370_REG_LED_SYS_CONFIG, RTL8370_LED_IO_DISABLE_OFFSET, 0)) != RT_ERR_OK)
|
||||
return retVal;
|
||||
|
||||
return RT_ERR_OK;
|
||||
}
|
||||
|
||||
int RTL8370_init()
|
||||
{
|
||||
rtk_portmask_t portmask;
|
||||
unsigned int ret; //, regData;
|
||||
|
||||
/* Set external interface 0 to RGMII with Force mode, 1000M, Full-duple, enable TX&RX pause*/
|
||||
rtk_port_mac_ability_t mac_cfg;
|
||||
rtk_mode_ext_t mode;
|
||||
|
||||
rtl8370_setAsicReg(RTL8370_REG_CHIP_RESET, (1 << RTL8370_CHIP_RST_OFFSET));
|
||||
// mdelay(1200);
|
||||
|
||||
/* Initial Chip */
|
||||
ret = rtk_switch_init();
|
||||
|
||||
/* Enable LED Group 0&1 from P0 to P7 */
|
||||
portmask.bits[0] = 0x0FF;
|
||||
rtk_led_enable_set(LED_GROUP_0, portmask);
|
||||
// rtk_led_enable_set(LED_GROUP_1, portmask);
|
||||
|
||||
/*
|
||||
port 0 ~ 7: Giga MAC/PHY (as LAN)
|
||||
MAC8 <--> GMAC 0 <--> rtk_port_macForceLinkExt1_set (Ext1) <--> 8211E (as WAN)
|
||||
MAC9 <--> GMAC 1 <--> rtk_port_macForceLinkExt0_set (Ext0) <--> 8197DN port 0
|
||||
*/
|
||||
/*mode = MODE_EXT_RGMII;
|
||||
mac_cfg.forcemode = MAC_FORCE;
|
||||
mac_cfg.speed = SPD_1000M;
|
||||
mac_cfg.duplex = FULL_DUPLEX;
|
||||
mac_cfg.link = PORT_LINKUP;
|
||||
mac_cfg.nway = DISABLED;
|
||||
mac_cfg.txpause = ENABLED;
|
||||
mac_cfg.rxpause = ENABLED;
|
||||
rtk_port_macForceLinkExt0_set(mode, &mac_cfg);*/
|
||||
|
||||
/* Set RGMII Interface 0 TX delay to 2ns and RX to step 4 */
|
||||
// set the tx/rx delay in 8197D site
|
||||
// rtk_port_rgmiiDelayExt1_set(0, 2); // change rxDelay to 2 to enhance the compatibility of 8197D and 8367RB
|
||||
rtk_port_rgmiiDelayExt0_set(0, 2);
|
||||
|
||||
// for port 8, 8211E port
|
||||
/* mode = MODE_EXT_RGMII;
|
||||
mac_cfg.forcemode = MAC_FORCE;
|
||||
mac_cfg.speed = SPD_1000M;
|
||||
mac_cfg.duplex = FULL_DUPLEX;
|
||||
mac_cfg.link = PORT_LINKUP;
|
||||
mac_cfg.nway = DISABLED;
|
||||
mac_cfg.txpause = ENABLED;
|
||||
mac_cfg.rxpause = ENABLED;
|
||||
rtk_port_macForceLinkExt1_set(mode, &mac_cfg);
|
||||
|
||||
rtk_port_rgmiiDelayExt1_set(1, 2);*/
|
||||
|
||||
/* set port 9 as CPU port */
|
||||
/*rtk_cpu_enable_set(ENABLE);
|
||||
rtk_cpu_tagPort_set(RTK_EXT_0_MAC, CPU_INSERT_TO_NONE);*/
|
||||
|
||||
// for LED
|
||||
rtl8370_setAsicReg(0x1b00, 0x1497);
|
||||
rtl8370_setAsicReg(0x1b24, 0x0);
|
||||
rtl8370_setAsicReg(0x1b25, 0x0);
|
||||
rtl8370_setAsicReg(0x1b26, 0x3);
|
||||
rtl8370_setAsicReg(0x1b03, 0x222);
|
||||
|
||||
// rtl8370_setAsicReg(RTL8370_REG_UNUCAST_FLOADING_PMSK, 0xff);
|
||||
// rtl8370_setAsicReg(RTL8370_REG_UNMCAST_FLOADING_PMSK, 0xff);
|
||||
// rtl8370_setAsicReg(RTL8370_REG_BCAST_FLOADING_PMSK, 0xff);
|
||||
|
||||
/* clear bit 2 of reg. RTL8370_REG_EXT0_RGMXF */
|
||||
// ret = rtl8370_getAsicReg(RTL8370_REG_EXT0_RGMXF, ®Data);
|
||||
// if(ret==RT_ERR_OK)
|
||||
// rtl8370_setAsicReg(RTL8370_REG_EXT0_RGMXF, (regData & ~0x4));
|
||||
|
||||
// for IGMP snooping
|
||||
// rtl8370_setAsicIpMulticastVlanLeaky(RTL8370_WAN,ENABLED);
|
||||
/*rtk_trap_unknownMcastPktAction_set(RTL8370_WAN, MCAST_IPV4, MCAST_ACTION_TRAP2CPU);
|
||||
|
||||
rtk_trap_igmpCtrlPktAction_set(IGMP_IPV4, IGMP_ACTION_TRAP2CPU);
|
||||
rtk_trap_igmpCtrlPktAction_set(IGMP_PPPOE_IPV4, IGMP_ACTION_TRAP2CPU);*/
|
||||
|
||||
// printk(" ==> RTL8370 initialized.\n");
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,195 @@
|
|||
/*
|
||||
* Copyright (C) 2009 Realtek Semiconductor Corp.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is the proprietary software of Realtek Semiconductor
|
||||
* Corporation and/or its licensors, and only be used, duplicated,
|
||||
* modified or distributed under the authorized license from Realtek.
|
||||
*
|
||||
* ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER
|
||||
* THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED.
|
||||
*
|
||||
* $Revision: 6658 $
|
||||
* $Date: 2009-10-30 14:49:58 +0800 (Fri, 30 Oct 2009) $
|
||||
*
|
||||
* Purpose : RTL8370 switch high-level API for RTL8367B
|
||||
* Feature :
|
||||
*
|
||||
*/
|
||||
#include <rtl8370_asicdrv.h>
|
||||
#include <smi.h>
|
||||
|
||||
/*=======================================================================
|
||||
* 1. Asic read/write driver through SMI
|
||||
*========================================================================*/
|
||||
/*
|
||||
@func ret_t | rtl8370_setAsicRegBit | Set a bit value of a specified register.
|
||||
@parm uint32 | reg | Register's address.
|
||||
@parm uint32 | bit | Bit location. For 16-bits register only. Maximun value is 15 for MSB location.
|
||||
@parm uint32 | value | Value to set. It can be value 0 or 1.
|
||||
@rvalue RT_ERR_OK | Success.
|
||||
@rvalue RT_ERR_SMI | SMI access error.
|
||||
@rvalue RT_ERR_INPUT | Invalid input parameter.
|
||||
@comm
|
||||
Set a bit of a specified register to 1 or 0. It is 16-bits system of RTL8366s chip.
|
||||
|
||||
*/
|
||||
ret_t rtl8370_setAsicRegBit(uint16 reg, int bit, uint16 value)
|
||||
{
|
||||
uint16 regData;
|
||||
ret_t retVal;
|
||||
|
||||
if (bit >= RTL8370_REGBITLENGTH)
|
||||
return RT_ERR_INPUT;
|
||||
|
||||
retVal = smi_read((uint16)reg, ®Data);
|
||||
if (retVal != RT_ERR_OK)
|
||||
return RT_ERR_SMI;
|
||||
if (value)
|
||||
regData = regData | (1 << bit);
|
||||
else
|
||||
regData = regData & (~(1 << bit));
|
||||
|
||||
retVal = smi_write((uint16)reg, regData);
|
||||
|
||||
if (retVal != RT_ERR_OK)
|
||||
return RT_ERR_SMI;
|
||||
|
||||
return RT_ERR_OK;
|
||||
}
|
||||
|
||||
ret_t rtl8370_getAsicRegBit(uint16 reg, int bit, uint16 *value)
|
||||
{
|
||||
|
||||
uint16 regData;
|
||||
ret_t retVal;
|
||||
|
||||
retVal = smi_read((uint16)reg, ®Data);
|
||||
if (retVal != RT_ERR_OK)
|
||||
return RT_ERR_SMI;
|
||||
|
||||
*value = (regData & (0x1 << bit)) >> bit;
|
||||
|
||||
return RT_ERR_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
@func ret_t | rtl8370_setAsicRegBits | Set bits value of a specified register.
|
||||
@parm uint32 | reg | Register's address.
|
||||
@parm uint32 | bits | Bits mask for setting.
|
||||
@parm uint32 | value | Bits value for setting. Value of bits will be set with mapping mask bit is 1.
|
||||
@rvalue RT_ERR_OK | Success.
|
||||
@rvalue RT_ERR_SMI | SMI access error.
|
||||
@rvalue RT_ERR_INPUT | Invalid input parameter.
|
||||
@comm
|
||||
Set bits of a specified register to value. Both bits and value are be treated as bit-mask.
|
||||
|
||||
*/
|
||||
ret_t rtl8370_setAsicRegBits(uint16 reg, int bits, uint16 value)
|
||||
{
|
||||
uint16 regData;
|
||||
ret_t retVal;
|
||||
uint32 bitsShift;
|
||||
uint32 valueShifted;
|
||||
|
||||
if (bits >= (1 << RTL8370_REGBITLENGTH))
|
||||
return RT_ERR_INPUT;
|
||||
|
||||
bitsShift = 0;
|
||||
while (!(bits & (1 << bitsShift)))
|
||||
{
|
||||
bitsShift++;
|
||||
if (bitsShift >= RTL8370_REGBITLENGTH)
|
||||
return RT_ERR_INPUT;
|
||||
}
|
||||
valueShifted = value << bitsShift;
|
||||
|
||||
if (valueShifted > RTL8370_REGDATAMAX)
|
||||
return RT_ERR_INPUT;
|
||||
|
||||
retVal = smi_read((uint16)reg, ®Data);
|
||||
if (retVal != RT_ERR_OK)
|
||||
return RT_ERR_SMI;
|
||||
|
||||
regData = regData & (~bits);
|
||||
regData = regData | (valueShifted & bits);
|
||||
|
||||
retVal = smi_write((uint16)reg, regData);
|
||||
if (retVal != RT_ERR_OK)
|
||||
return RT_ERR_SMI;
|
||||
|
||||
return RT_ERR_OK;
|
||||
}
|
||||
|
||||
ret_t rtl8370_getAsicRegBits(uint16 reg, int bits, uint16 *value)
|
||||
{
|
||||
|
||||
uint32 regData;
|
||||
ret_t retVal;
|
||||
uint32 bitsShift;
|
||||
|
||||
if (bits >= (1 << RTL8370_REGBITLENGTH))
|
||||
return RT_ERR_INPUT;
|
||||
|
||||
bitsShift = 0;
|
||||
while (!(bits & (1 << bitsShift)))
|
||||
{
|
||||
bitsShift++;
|
||||
if (bitsShift >= RTL8370_REGBITLENGTH)
|
||||
return RT_ERR_INPUT;
|
||||
}
|
||||
|
||||
retVal = smi_read((uint16)reg, ®Data);
|
||||
if (retVal != RT_ERR_OK)
|
||||
return RT_ERR_SMI;
|
||||
|
||||
*value = (regData & bits) >> bitsShift;
|
||||
|
||||
return RT_ERR_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
@func ret_t | rtl8370_setAsicReg | Set content of asic register.
|
||||
@parm uint32 | reg | Register's address.
|
||||
@parm uint32 | value | Value setting to register.
|
||||
@rvalue RT_ERR_OK | Success.
|
||||
@rvalue RT_ERR_SMI | SMI access error.
|
||||
@comm
|
||||
The value will be set to ASIC mapping address only and it is always return RT_ERR_OK while setting un-mapping address registers.
|
||||
|
||||
*/
|
||||
ret_t rtl8370_setAsicReg(uint16 reg, uint16 value)
|
||||
{
|
||||
ret_t retVal;
|
||||
|
||||
retVal = smi_write(reg, value);
|
||||
if (retVal != RT_ERR_OK)
|
||||
return RT_ERR_SMI;
|
||||
|
||||
return RT_ERR_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
@func ret_t | rtl8370_getAsicReg | Get content of register.
|
||||
@parm uint32 | reg | Register's address.
|
||||
@parm uint32* | value | Value of register.
|
||||
@rvalue RT_ERR_OK | Success.
|
||||
@rvalue RT_ERR_SMI | SMI access error.
|
||||
@comm
|
||||
Value 0x0000 will be returned for ASIC un-mapping address.
|
||||
|
||||
*/
|
||||
ret_t rtl8370_getAsicReg(uint16 reg, uint16 *value)
|
||||
{
|
||||
|
||||
uint16 regData;
|
||||
ret_t retVal;
|
||||
|
||||
retVal = smi_read(reg, ®Data);
|
||||
if (retVal != RT_ERR_OK)
|
||||
return RT_ERR_SMI;
|
||||
|
||||
*value = regData;
|
||||
|
||||
return RT_ERR_OK;
|
||||
}
|
||||
|
|
@ -0,0 +1,147 @@
|
|||
/*
|
||||
* Copyright (C) 2009 Realtek Semiconductor Corp.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is the proprietary software of Realtek Semiconductor
|
||||
* Corporation and/or its licensors, and only be used, duplicated,
|
||||
* modified or distributed under the authorized license from Realtek.
|
||||
*
|
||||
* ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER
|
||||
* THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED.
|
||||
*
|
||||
* $Revision: 6927 $
|
||||
* $Date: 2009-11-10 19:12:30 +0800 (Tue, 10 Nov 2009) $
|
||||
*
|
||||
* Purpose : RTL8370 switch high-level API for RTL8367B
|
||||
* Feature :
|
||||
*
|
||||
*/
|
||||
#include "rtl8370_asicdrv.h"
|
||||
#include "rtl8370_asicdrv_phy.h"
|
||||
|
||||
/*
|
||||
@func ret_t | rtl8370_setAsicPHYReg | Set PHY registers .
|
||||
@parm uint32 | phyNo | PHY number (0~7).
|
||||
@parm uint32 | phyAddr | PHY address (0~31).
|
||||
@parm uint32 | data | Writing data.
|
||||
@rvalue RT_ERR_OK |
|
||||
@rvalue RT_ERR_FAILED | invalid parameter
|
||||
@rvalue RT_ERR_PHY_REG_ID | invalid PHY address
|
||||
@rvalue RT_ERR_PORT_ID | invalid port id.
|
||||
@rvalue RT_ERR_BUSYWAIT_TIMEOUT | PHY access busy
|
||||
@comm
|
||||
The API can set internal PHY register 0~31. There are 8 internal PHYs in switch and each PHY can be
|
||||
accessed by software.
|
||||
*/
|
||||
ret_t rtl8370_setAsicPHYReg(int phyNo, int phyAddr, uint16 data)
|
||||
{
|
||||
ret_t retVal;
|
||||
uint16 regData;
|
||||
uint16 busyFlag;
|
||||
|
||||
if (phyNo > RTL8370_PHY_INTERNALNOMAX)
|
||||
return RT_ERR_PORT_ID;
|
||||
|
||||
if (phyAddr > RTL8370_PHY_REGNOMAX)
|
||||
return RT_ERR_PHY_REG_ID;
|
||||
|
||||
/*
|
||||
word address a[15] a[14] a[13] a[12] a[11] a[10] a[9] a[8] a[7] a[6] a[5] a[4] a[3] a[2] a[1] a[0]
|
||||
phy0 ~ phy7 [ 3'd1 ] [ 0 0 0 0 0 ] [ PHY No. ] [ reg adr[4:0] ]
|
||||
*/
|
||||
|
||||
/*Check internal phy access busy or not*/
|
||||
retVal = rtl8370_getAsicRegBit(RTL8370_REG_INDRECT_ACCESS_STATUS, RTL8370_PHY_BUSY_OFFSET, &busyFlag);
|
||||
if (retVal != RT_ERR_OK)
|
||||
return retVal;
|
||||
|
||||
if (busyFlag)
|
||||
return RT_ERR_BUSYWAIT_TIMEOUT;
|
||||
|
||||
/*prepare access data*/
|
||||
retVal = rtl8370_setAsicReg(RTL8370_REG_INDRECT_ACCESS_WRITE_DATA, data);
|
||||
if (retVal != RT_ERR_OK)
|
||||
return retVal;
|
||||
|
||||
/*prepare access address*/
|
||||
regData = RTL8370_PHY_BASE | (phyNo << RTL8370_PHY_OFFSET) | phyAddr;
|
||||
|
||||
retVal = rtl8370_setAsicReg(RTL8370_REG_INDRECT_ACCESS_ADDRESS, regData);
|
||||
if (retVal != RT_ERR_OK)
|
||||
return retVal;
|
||||
|
||||
/*Set WRITE Command*/
|
||||
return rtl8370_setAsicReg(RTL8370_REG_INDRECT_ACCESS_CRTL, RTL8370_CMD_MASK | RTL8370_RW_MASK);
|
||||
}
|
||||
|
||||
/*
|
||||
@func ret_t | rtl8370_getAsicPHYReg | Set PHY registers.
|
||||
@parm uint32 | phyNo | PHY number (0~7).
|
||||
@parm uint32 | phyAddr | PHY address (0~31).
|
||||
@parm uint32* | data | Read data.
|
||||
@rvalue RT_ERR_OK |
|
||||
@rvalue RT_ERR_FAILED | invalid parameter
|
||||
@rvalue RT_ERR_PHY_REG_ID | invalid PHY address
|
||||
@rvalue RT_ERR_PORT_ID | iinvalid port id
|
||||
@rvalue RT_ERR_BUSYWAIT_TIMEOUT | PHY access busy
|
||||
@comm
|
||||
The API can get internal PHY register 0~31. There are 8 internal PHYs in switch and each PHY can be
|
||||
accessed by software.
|
||||
*/
|
||||
ret_t rtl8370_getAsicPHYReg(int phyNo, int phyAddr, uint16 *data)
|
||||
{
|
||||
ret_t retVal;
|
||||
uint16 regData;
|
||||
uint16 busyFlag, checkCounter;
|
||||
|
||||
if (phyNo > RTL8370_PHY_INTERNALNOMAX)
|
||||
return RT_ERR_PORT_ID;
|
||||
|
||||
if (phyAddr > RTL8370_PHY_REGNOMAX)
|
||||
return RT_ERR_PHY_REG_ID;
|
||||
|
||||
/*Check internal phy access busy or not*/
|
||||
retVal = rtl8370_getAsicRegBit(RTL8370_REG_INDRECT_ACCESS_STATUS, RTL8370_PHY_BUSY_OFFSET, &busyFlag);
|
||||
if (retVal != RT_ERR_OK)
|
||||
return retVal;
|
||||
|
||||
if (busyFlag)
|
||||
return RT_ERR_BUSYWAIT_TIMEOUT;
|
||||
|
||||
/*prepare access address*/
|
||||
regData = RTL8370_PHY_BASE | (phyNo << RTL8370_PHY_OFFSET) | phyAddr;
|
||||
|
||||
retVal = rtl8370_setAsicReg(RTL8370_REG_INDRECT_ACCESS_ADDRESS, regData);
|
||||
if (retVal != RT_ERR_OK)
|
||||
return retVal;
|
||||
|
||||
/*Set READ Command*/
|
||||
retVal = rtl8370_setAsicReg(RTL8370_REG_INDRECT_ACCESS_CRTL, RTL8370_CMD_MASK);
|
||||
if (retVal != RT_ERR_OK)
|
||||
return retVal;
|
||||
|
||||
checkCounter = 5;
|
||||
while (checkCounter)
|
||||
{
|
||||
retVal = rtl8370_getAsicRegBit(RTL8370_REG_INDRECT_ACCESS_STATUS, RTL8370_PHY_BUSY_OFFSET, &busyFlag);
|
||||
if (retVal != RT_ERR_OK)
|
||||
{
|
||||
checkCounter--;
|
||||
if (0 == checkCounter)
|
||||
return retVal;
|
||||
}
|
||||
else
|
||||
{
|
||||
checkCounter = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/*get PHY register*/
|
||||
retVal = rtl8370_getAsicReg(RTL8370_REG_INDRECT_ACCESS_READ_DATA, ®Data);
|
||||
if (retVal != RT_ERR_OK)
|
||||
return retVal;
|
||||
|
||||
*data = regData;
|
||||
|
||||
return RT_ERR_OK;
|
||||
}
|
||||
|
|
@ -0,0 +1,146 @@
|
|||
/*
|
||||
* Copyright Sistematics Inc, 2023
|
||||
* All rights reserved.
|
||||
*
|
||||
* Program : Control RTL8370N connected to I2C-like bus.
|
||||
* It is called SMI because this I2C-like protocol emulates SMI bus using I2C protocol.
|
||||
*/
|
||||
|
||||
#include <Arduino.h>
|
||||
#include "smi.h"
|
||||
|
||||
#define I2C_DELAY_MS 2
|
||||
|
||||
static uint8 switch_addr;
|
||||
static int pin_data;
|
||||
static int pin_clk;
|
||||
|
||||
void i2c_start()
|
||||
{
|
||||
digitalWrite(pin_data, HIGH);
|
||||
digitalWrite(pin_clk, HIGH);
|
||||
delayMicroseconds(I2C_DELAY_MS);
|
||||
digitalWrite(pin_data, LOW);
|
||||
delayMicroseconds(I2C_DELAY_MS);
|
||||
digitalWrite(pin_clk, LOW);
|
||||
delayMicroseconds(I2C_DELAY_MS);
|
||||
}
|
||||
|
||||
void i2c_stop()
|
||||
{
|
||||
digitalWrite(pin_clk, LOW);
|
||||
delayMicroseconds(I2C_DELAY_MS);
|
||||
digitalWrite(pin_data, LOW);
|
||||
delayMicroseconds(I2C_DELAY_MS);
|
||||
digitalWrite(pin_clk, HIGH);
|
||||
delayMicroseconds(I2C_DELAY_MS);
|
||||
digitalWrite(pin_data, HIGH);
|
||||
delayMicroseconds(I2C_DELAY_MS);
|
||||
}
|
||||
|
||||
// Emulated I2C send byte
|
||||
bool i2c_send_byte(unsigned char data)
|
||||
{
|
||||
for (int i = 0; i < 8; i++)
|
||||
{
|
||||
digitalWrite(pin_data, (data & (1 << (7 - i))) != 0);
|
||||
delayMicroseconds(I2C_DELAY_MS);
|
||||
digitalWrite(pin_clk, HIGH);
|
||||
delayMicroseconds(I2C_DELAY_MS);
|
||||
digitalWrite(pin_clk, LOW);
|
||||
delayMicroseconds(I2C_DELAY_MS);
|
||||
}
|
||||
// Receive ACK
|
||||
digitalWrite(pin_data, HIGH);
|
||||
pinMode(pin_data, INPUT);
|
||||
digitalWrite(pin_clk, HIGH);
|
||||
delayMicroseconds(I2C_DELAY_MS);
|
||||
bool ack = digitalRead(pin_data) == LOW;
|
||||
digitalWrite(pin_clk, LOW);
|
||||
delayMicroseconds(I2C_DELAY_MS);
|
||||
pinMode(pin_data, OUTPUT);
|
||||
return ack;
|
||||
}
|
||||
|
||||
uint8 i2c_read_byte(bool ack)
|
||||
{
|
||||
uint8 data = 0;
|
||||
digitalWrite(pin_data, HIGH);
|
||||
pinMode(pin_data, INPUT);
|
||||
for (int i = 0; i < 8; i++)
|
||||
{
|
||||
digitalWrite(pin_clk, HIGH);
|
||||
delayMicroseconds(I2C_DELAY_MS);
|
||||
data |= digitalRead(pin_data) << (7 - i);
|
||||
digitalWrite(pin_clk, LOW);
|
||||
delayMicroseconds(I2C_DELAY_MS);
|
||||
}
|
||||
pinMode(pin_data, OUTPUT);
|
||||
digitalWrite(pin_data, !ack);
|
||||
delayMicroseconds(I2C_DELAY_MS);
|
||||
digitalWrite(pin_clk, HIGH);
|
||||
delayMicroseconds(I2C_DELAY_MS);
|
||||
digitalWrite(pin_clk, LOW);
|
||||
delayMicroseconds(I2C_DELAY_MS);
|
||||
return data;
|
||||
}
|
||||
|
||||
int smi_write(uint16 reg, uint16 data)
|
||||
{
|
||||
uint8 addr = switch_addr;
|
||||
i2c_start();
|
||||
// Send addr with RW bit = 0
|
||||
if (!i2c_send_byte(addr << 1))
|
||||
return RT_ERR_SMI;
|
||||
// Send first byte of the reg
|
||||
if (!i2c_send_byte((uint8)(reg & 0xFF)))
|
||||
return RT_ERR_SMI;
|
||||
// Send second byte of the reg
|
||||
if (!i2c_send_byte((uint8)(reg >> 8)))
|
||||
return RT_ERR_SMI;
|
||||
// Send first byte of the data
|
||||
if (!i2c_send_byte((uint8)(data & 0xFF)))
|
||||
return RT_ERR_SMI;
|
||||
// Send second byte of the data
|
||||
if (!i2c_send_byte((uint8)(data >> 8)))
|
||||
return RT_ERR_SMI;
|
||||
i2c_stop();
|
||||
return RT_ERR_OK;
|
||||
}
|
||||
|
||||
int smi_read(uint16 reg, uint16 *data)
|
||||
{
|
||||
uint8 addr = switch_addr;
|
||||
uint8 val = 0;
|
||||
i2c_start();
|
||||
// Send addr with RW bit = 1
|
||||
if (!i2c_send_byte(addr << 1 | 0x1))
|
||||
return RT_ERR_SMI;
|
||||
|
||||
// Send first byte of the reg
|
||||
if (!i2c_send_byte((uint8)(reg & 0xFF)))
|
||||
return RT_ERR_SMI;
|
||||
// Send second byte of the reg
|
||||
if (!i2c_send_byte((uint8)(reg >> 8)))
|
||||
return RT_ERR_SMI;
|
||||
|
||||
val = i2c_read_byte(true);
|
||||
*data |= val;
|
||||
val = i2c_read_byte(false);
|
||||
*data |= (val << 8);
|
||||
|
||||
i2c_stop();
|
||||
return RT_ERR_OK;
|
||||
}
|
||||
|
||||
int smi_init(uint8 pinSCK, uint8 pinSDA, uint8 switchAddr)
|
||||
{
|
||||
switch_addr = switchAddr;
|
||||
pin_clk = pinSCK;
|
||||
pin_data = pinSDA;
|
||||
pinMode(pin_data, OUTPUT);
|
||||
pinMode(pin_clk, OUTPUT);
|
||||
digitalWrite(pin_data, HIGH);
|
||||
digitalWrite(pin_clk, HIGH);
|
||||
return RT_ERR_OK;
|
||||
}
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
#include <Arduino.h>
|
||||
#include "board.h"
|
||||
#include "switch.h"
|
||||
#include "smi.h"
|
||||
#include "rtk_api.h"
|
||||
|
||||
/**
|
||||
* Performs hard reset of the RTL8370N chip
|
||||
*/
|
||||
void switch_hard_reset(int newState)
|
||||
{
|
||||
if (newState == 0)
|
||||
{
|
||||
digitalWrite(SWITCH_RESET, HIGH);
|
||||
}
|
||||
else
|
||||
{
|
||||
digitalWrite(SWITCH_RESET, LOW);
|
||||
}
|
||||
|
||||
delay(100);
|
||||
}
|
||||
|
||||
rtk_api_ret_t switch_init()
|
||||
{
|
||||
smi_init(SWITCH_CLK, SWITCH_DATA, SWITCH_ADDR);
|
||||
RTL8370_init();
|
||||
return RT_ERR_OK;
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
|
||||
This directory is intended for PlatformIO Test Runner and project tests.
|
||||
|
||||
Unit Testing is a software testing method by which individual units of
|
||||
source code, sets of one or more MCU program modules together with associated
|
||||
control data, usage procedures, and operating procedures, are tested to
|
||||
determine whether they are fit for use. Unit testing finds problems early
|
||||
in the development cycle.
|
||||
|
||||
More information about PlatformIO Unit Testing:
|
||||
- https://docs.platformio.org/en/latest/advanced/unit-testing/index.html
|
||||
Loading…
Reference in New Issue