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GigaDevice_test
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Modified PLL2 out

This commit is contained in:
Alexey Bazlaev 2023-02-02 19:19:49 +07:00
parent e9acfe19a2
commit a216f29ef2
3 changed files with 91 additions and 124 deletions
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170
Test_project_for_GD32107C-EVAL.uvguix.right
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File diff suppressed because one or more lines are too long

23
Test_project_for_GD32107C-EVAL.uvoptx
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@ -175,10 +175,31 @@
<Mm>
<WinNumber>1</WinNumber>
<SubType>0</SubType>
<ItemText>0x40011000</ItemText>
<ItemText>0x40028014</ItemText>
<AccSizeX>0</AccSizeX>
</Mm>
</MemoryWindow1>
<MemoryWindow2>
<Mm>
<WinNumber>2</WinNumber>
<SubType>0</SubType>
<ItemText>0x20001FCC</ItemText>
<AccSizeX>0</AccSizeX>
</Mm>
</MemoryWindow2>
<MemoryWindow3>
<Mm>
<WinNumber>3</WinNumber>
<SubType>0</SubType>
<ItemText>reg</ItemText>
<AccSizeX>0</AccSizeX>
</Mm>
</MemoryWindow3>
<ScvdPack>
<Filename>C:\Users\User\AppData\Local\Arm\Packs\ARM\CMSIS-FreeRTOS\10.5.1\CMSIS\RTOS2\FreeRTOS\FreeRTOS.scvd</Filename>
<Type>ARM.CMSIS-FreeRTOS.10.5.1</Type>
<SubType>1</SubType>
</ScvdPack>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>

22
main.c
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@ -32,6 +32,7 @@
#define RMII_REF_CLK_PORT GPIOA
#define RMII_REF_CLK GPIO_PIN_1
#define MCO GPIO_PIN_8
#define RMII_MDC_PORT GPIOC
#define RMII_MDC GPIO_PIN_1
@ -167,7 +168,7 @@ static ErrStatus vInitPLL2(void)
/* enable PLL2 */
RCU_CTL |= RCU_CTL_PLL2EN;
/* wait till PLL2 is ready */
while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){
while(RESET == rcu_flag_get(RCU_FLAG_PLL2STB)){
};
return SUCCESS;
}
@ -183,7 +184,10 @@ static void vInitMCU(void)
rcu_periph_clock_enable(RCU_GPIOB);
rcu_periph_clock_enable(RCU_GPIOC);
rcu_periph_clock_enable(RCU_GPIOE);
rcu_periph_clock_enable(RCU_AF);
rcu_periph_clock_enable(RCU_ENET);
rcu_periph_clock_enable(RCU_ENETTX);
rcu_periph_clock_enable(RCU_ENETRX);
/*Enable PLL2 to generate 50MHz clocks */
if (ERROR == vInitPLL2())
{
@ -194,14 +198,7 @@ static void vInitMCU(void)
}
/*Put PLL2 clocks into CKOUT0(PA1) as ref clock for ethernet phy*/
rcu_ckout0_config(RCU_CKOUT0SRC_CKPLL2);
//rcu_periph_clock_enable(RCU_AF);
rcu_periph_clock_enable(RCU_ENET);
rcu_periph_clock_enable(RCU_ENETTX);
rcu_periph_clock_enable(RCU_ENETRX);
//rcu_periph_reset_enable(RCU_ENETRST);
rcu_ckout0_config(RCU_CKOUT0SRC_CKPLL2);
gpio_ethernet_phy_select(GPIO_ENET_PHY_RMII);
/*
* Configure GPIO Alternate RMII function
@ -213,12 +210,15 @@ static void vInitMCU(void)
gpio_init(RMII_MDC_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, RMII_MDC);
gpio_init(RMII_MDIO_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, RMII_MDIO);
gpio_init(RMII_INT_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, RMII_INT);
gpio_init(RMII_REF_CLK_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, RMII_REF_CLK);
gpio_init(RMII_REF_CLK_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, RMII_REF_CLK);
gpio_init(RMII_REF_CLK_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, MCO);
//gpio_init(RMII_RXD_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, RMII_RXD0);
//gpio_init(RMII_RXD_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, RMII_RXD1);
//gpio_init(RMII_CRS_DV_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, RMII_CRS_DV);
/*
* Configure GPIO Output function for LEDs
*/