abazlaev
/
GigaDevice_test
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Enabled PLL2

This commit is contained in:
Alexei 2023-02-02 01:57:21 +07:00
parent cc590fa6aa
commit e9acfe19a2
3 changed files with 41 additions and 72 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
RTE/Device/GD32F107VC/system_gd32f10x.c
View File

@ -49,14 +49,14 @@ OF SUCH DAMAGE.
//#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000)
/* use HXTAL (XD series CK_HXTAL = 8M, CL series CK_HXTAL = 25M) */
#define __SYSTEM_CLOCK_HXTAL (uint32_t)(__HXTAL)
//#define __SYSTEM_CLOCK_HXTAL (uint32_t)(__HXTAL)
//#define __SYSTEM_CLOCK_24M_PLL_HXTAL (uint32_t)(24000000)
//#define __SYSTEM_CLOCK_36M_PLL_HXTAL (uint32_t)(36000000)
//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000)
//#define __SYSTEM_CLOCK_56M_PLL_HXTAL (uint32_t)(56000000)
//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000)
//#define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000)
//#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000)
#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000)
#define SEL_IRC8M 0x00U
#define SEL_HXTAL 0x01U

58
Test_project_for_GD32107C-EVAL.uvoptx
View File

@ -153,40 +153,7 @@
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL040000 -FP0($$Device:GD32F107VC$Flash\GD32F10x_CL.FLM))</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint>
<Bp>
<Number>0</Number>
<Type>0</Type>
<LineNumber>163</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>134268292</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>.\main.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\Test_project_for_GD32107C_EVAL\main.c\163</Expression>
</Bp>
<Bp>
<Number>1</Number>
<Type>0</Type>
<LineNumber>171</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>134268332</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>.\main.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\Test_project_for_GD32107C_EVAL\main.c\171</Expression>
</Bp>
</Breakpoint>
<Breakpoint/>
<WatchWindow1>
<Ww>
<count>0</count>
@ -208,31 +175,10 @@
<Mm>
<WinNumber>1</WinNumber>
<SubType>0</SubType>
<ItemText>0x40028014</ItemText>
<ItemText>0x40011000</ItemText>
<AccSizeX>0</AccSizeX>
</Mm>
</MemoryWindow1>
<MemoryWindow2>
<Mm>
<WinNumber>2</WinNumber>
<SubType>0</SubType>
<ItemText>0x20001FCC</ItemText>
<AccSizeX>0</AccSizeX>
</Mm>
</MemoryWindow2>
<MemoryWindow3>
<Mm>
<WinNumber>3</WinNumber>
<SubType>0</SubType>
<ItemText>reg</ItemText>
<AccSizeX>0</AccSizeX>
</Mm>
</MemoryWindow3>
<ScvdPack>
<Filename>C:\Users\User\AppData\Local\Arm\Packs\ARM\CMSIS-FreeRTOS\10.5.1\CMSIS\RTOS2\FreeRTOS\FreeRTOS.scvd</Filename>
<Type>ARM.CMSIS-FreeRTOS.10.5.1</Type>
<SubType>1</SubType>
</ScvdPack>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>

51
main.c
View File

@ -155,20 +155,46 @@ int stdin_getchar (void)
return usart_data_receive(EVAL_COM1);
}
/**! \brief vInitPLL2(void)
* Enable PLL2 to generate 50MHz clocks
*/
static ErrStatus vInitPLL2(void)
{
/*CK_PREDIV1 = (CK_HXTAL)/5 = 5 MHz */
if (!(RCU_CFG1 & RCU_PREDV1_DIV5)) return ERROR;
/* CK_PLL2 = (CK_PREDIV1) * 10 = 50 MHz */
rcu_pll2_config(RCU_PLL2_MUL10);
/* enable PLL2 */
RCU_CTL |= RCU_CTL_PLL2EN;
/* wait till PLL2 is ready */
while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){
};
return SUCCESS;
}
/**! \brief vInitMCU
* Initial MCU configuration
*/
static void vInitMCU(void)
{
SystemInit();
//gd_eval_led_init(LED2);
//gd_eval_led_on(LED2);
rcu_periph_clock_enable(RCU_GPIOA);
rcu_periph_clock_enable(RCU_GPIOB);
rcu_periph_clock_enable(RCU_GPIOC);
rcu_periph_clock_enable(RCU_GPIOE);
rcu_ckout0_config(RCU_CKOUT0SRC_HXTAL);
/*Enable PLL2 to generate 50MHz clocks */
if (ERROR == vInitPLL2())
{
#if defined (DEBUG)
printf("PLL2 initialization failed\n");
__ASM("BKPT #0\n");
#endif
}
/*Put PLL2 clocks into CKOUT0(PA1) as ref clock for ethernet phy*/
rcu_ckout0_config(RCU_CKOUT0SRC_CKPLL2);
//rcu_periph_clock_enable(RCU_AF);
rcu_periph_clock_enable(RCU_ENET);
@ -183,24 +209,21 @@ static void vInitMCU(void)
gpio_init(RMII_TXD_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, RMII_TX_EN);
gpio_init(RMII_TXD_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, RMII_TXD0);
gpio_init(RMII_TXD_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, RMII_TXD1);
gpio_init(RMII_MDC_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, RMII_MDC);
gpio_init(RMII_MDIO_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, RMII_MDIO);
gpio_init(RMII_INT_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, RMII_INT);
gpio_init(RMII_REF_CLK_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, RMII_REF_CLK);
//gpio_init(RMII_RXD_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, RMII_RXD0);
//gpio_init(RMII_RXD_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, RMII_RXD1);
//gpio_init(RMII_CRS_DV_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, RMII_CRS_DV);
gpio_init(RMII_MDC_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, RMII_MDC);
gpio_init(RMII_MDIO_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, RMII_MDIO);
gpio_init(RMII_INT_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, RMII_INT);
gpio_init(RMII_REF_CLK_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, RMII_REF_CLK);
/*
* Configure GPIO Output function for LEDs
*/
gpio_init(LED2_USER_PORT, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, LED2_USER);
gpio_bit_set(LED2_USER_PORT, LED2_USER);
*/
gpio_init(LED2_USER_PORT, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, LED2_USER); //gd_eval_led_init(LED2);
gpio_bit_set(LED2_USER_PORT, LED2_USER); //gd_eval_led_on(LED2);
gpio_init(LED5_TICK_PORT, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, LED5_TICK);
gpio_bit_set(LED5_TICK_PORT, LED5_TICK);