Added STM32 networkinterface port

DemoTasks/SimpleTCPEchoServer.c

@@ -316,12 +316,12 @@ uint8_t *pucRxBuffer;
 				if (!strcmp("RF_ON", (char*)pucRxBuffer))
 				{					
 					vRFSwitchEnable(&rfSwitchConfig);
-					enable = true;
+					enable = pdTRUE;
 				}
 				else if (!strcmp("RF_OFF", (char*)pucRxBuffer))
 				{
 					vRFSwitchDisable(&rfSwitchConfig);
-					enable = false;
+					enable = pdFALSE;
 				}
 				else if (!strcmp("RF01", (char*)pucRxBuffer))
 					state = xRFSwitchSet(&rfSwitchConfig, RF_OUT_01);					

Doc/READ-COM3.ps1

@@ -1,10 +0,0 @@
-function read-com {
-$port= new-Object System.IO.Ports.SerialPort COM3,115200,None,8,one
-$port.Open()
-do {
-     $line = $port.ReadLine()
-     Write-Host $line # Do stuff here
-   }
-while ($port.IsOpen)
-}
-read-com

FreeRTOS/source/include/FreeRTOSIPConfig.h

@@ -38,7 +38,7 @@
 /* It is not sensible for this macro to have a default value as it is hardware
  * dependent. */
 #define ipconfigBYTE_ORDER    pdFREERTOS_LITTLE_ENDIAN
-#define ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS 	45
+#define ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS 	4
 #define ipconfigUSE_NETWORK_EVENT_HOOK 					1
 #define ipconfigUSE_DHCP    										1
 #define ipconfigUSE_DHCP_HOOK 									1

FreeRTOS/source/include/IPTraceMacro.h

@@ -6,7 +6,7 @@
 //#define iptraceNETWORK_DOWN() 					FreeRTOS_debug_printf(("[IPTRACE] Network down\nFreeHeapSize = %d\n", xPortGetFreeHeapSize()));
 																				
 
-#define iptraceSENDING_DNS_REQUEST() 		FreeRTOS_debug_printf(("[IPTRACE] Sending DNS request\nFreeHeapSize = %d\n", xPortGetFreeHeapSize()));
+//#define iptraceSENDING_DNS_REQUEST() 		FreeRTOS_debug_printf(("[IPTRACE] Sending DNS request\nFreeHeapSize = %d\n", xPortGetFreeHeapSize()));
 																				
 
 //#define iptraceSENDING_DHCP_DISCOVER() 	FreeRTOS_debug_printf(("[IPTRACE] Sending DHCP discover\nFreeHeapSize = %d\n", xPortGetFreeHeapSize()));

FreeRTOS/source/include/NetworkInterface.h

@@ -304,7 +304,16 @@ typedef struct
 		uint32_t buffer;               /*!< Frame buffer */
 } ETH_DMARxFrameInfos;
 
-#define ETH_TypeDef    void
+typedef struct
+{
+	uint32_t DMAIER;
+	uint32_t DMATDLAR;
+	uint32_t DMARDLAR;
+	uint32_t DMATPDR;
+	uint32_t DMASR;
+	uint32_t DMARPDR;
+} ETH_TypeDef;
+
 typedef  uint8_t HAL_LockTypeDef;
 /**
  * @brief  ETH Handle Structure definition

FreeRTOS/source/portable/NetworkInterface/board_family/NetworkInterface.c

@@ -76,9 +76,9 @@
 #include "NetworkBufferManagement.h"
 #include "NetworkInterface.h"
 
-#include "Driver_ETH.h"
+//#include "Driver_ETH.h"
-#include "Driver_ETH_MAC.h"
+//#include "Driver_ETH_MAC.h"
-#include "Driver_ETH_PHY.h"
+//#include "Driver_ETH_PHY.h"
 #include "gd32f10x_enet.h"
 #include "PHY_DP83848C.h"
 
@@ -466,7 +466,7 @@ int32_t ARM_ETH_MAC_ControlTimer (uint32_t control, ARM_ETH_MAC_TIME *time)
 */
 int32_t ARM_ETH_MAC_PHY_Read (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
 {
-	if((phy_addr >= 0) & (reg_addr >= 0x00) & data >= 0x0000)
+	if((phy_addr >= 0) & (reg_addr >= 0x00) & data > 0x0000)
 	{
 		if(SUCCESS == enet_phy_write_read(ENET_PHY_READ, phy_addr, reg_addr, data))
 			return ARM_DRIVER_OK;
@@ -1054,8 +1054,8 @@ void PendedReceiveHandler( void *pvParameter1, uint32_t ulParameter2 )
 //#include "stm32fxx_hal_eth.h"
 
 #include "Driver_ETH.h"
-/*#include "Driver_ETH_MAC.h"
+//#include "Driver_ETH_MAC.h"
-#include "Driver_ETH_PHY.h"*/
+//#include "Driver_ETH_PHY.h"
 /* If ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES is set to 1, then the Ethernet
  * driver will filter incoming packets and only pass the stack those packets it
  * considers need processing. */
@@ -1065,28 +1065,6 @@ void PendedReceiveHandler( void *pvParameter1, uint32_t ulParameter2 )
     #define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer )    eConsiderFrameForProcessing( ( pucEthernetBuffer ) )
 #endif
 
-
-BaseType_t xNetworkInterfaceOutput( NetworkBufferDescriptor_t * const pxNetworkBuffer,
-                                    BaseType_t xReleaseAfterSend )
-{
-    /* FIX ME. */
-    return pdFALSE;
-}
-
-void vNetworkInterfaceAllocateRAMToBuffers( NetworkBufferDescriptor_t pxNetworkBuffers[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ] )
-{
-    /* FIX ME. */
-}
-
-BaseType_t xGetPhyLinkStatus( void )
-{
-    /* FIX ME. */
-    return pdFALSE;
-}
-
-
-
-
 /* ST includes. */
 #if defined( GD32F10X_CL )
 		#include "gd32f10x_enet.h"
@@ -1112,6 +1090,9 @@ BaseType_t xGetPhyLinkStatus( void )
 #define EMAC_IF_ERR_EVENT       4UL
 #define EMAC_IF_ALL_EVENT       ( EMAC_IF_RX_EVENT | EMAC_IF_TX_EVENT | EMAC_IF_ERR_EVENT )
 
+#ifndef ETH_MAX_PACKET_SIZE
+	#define ETH_MAX_PACKET_SIZE ENET_MAX_FRAME_SIZE
+#endif
 /* Calculate the maximum packet size that the DMA can receive. */
 #define EMAC_DMA_BUFFER_SIZE    ( ( uint32_t ) ( ETH_MAX_PACKET_SIZE - ipBUFFER_PADDING ) )
 
@@ -1451,20 +1432,31 @@ static void vClearTXBuffers()
     }
 }
 /*-----------------------------------------------------------*/
-#warning Check HAL_StatusTypeDef/ETH/ETH_AUTONEGOTIATION_ENABLE/ETH_SPEED_100M/ETH_MODE_FULLDUPLEX/ETH_RXINTERRUPT_MODE/ETH_CHECKSUM_BY_SOFTWARE/ETH_MEDIA_INTERFACE_RMII
+#warning Check HAL_StatusTypeDef / ETH / ETH_AUTONEGOTIATION_ENABLE / ETH_SPEED_100M / ETH_MODE_FULLDUPLEX / ETH_RXINTERRUPT_MODE / ETH_CHECKSUM_BY_SOFTWARE / ETH_MEDIA_INTERFACE_RMII
-#define HAL_StatusTypeDef bool
+#define HAL_StatusTypeDef int8_t
+#define HAL_OK ARM_DRIVER_OK
 #define ETH (void*)ENET	
+	
 #ifndef ETH_AUTONEGOTIATION_ENABLE
 	#define ETH_AUTONEGOTIATION_ENABLE  ENET_AUTO_NEGOTIATION
 #endif
+
 #ifndef ETH_SPEED_100M
 	#define ETH_SPEED_100M  ENET_100M_FULLDUPLEX
 #endif
 
+#ifndef ETH_SPEED_10M
+	#define ETH_SPEED_10M  ENET_10M_FULLDUPLEX
+#endif
+
 #ifndef ETH_MODE_FULLDUPLEX
 	#define ETH_MODE_FULLDUPLEX  ENET_100M_FULLDUPLEX
 #endif
 
+#ifndef ETH_MODE_HALFDUPLEX
+	#define ETH_MODE_HALFDUPLEX ENET_100M_HALFDUPLEX
+#endif
+
 #ifndef ETH_RXINTERRUPT_MODE
 	#define ETH_RXINTERRUPT_MODE  ENET_DMA_INTEN_RIE|ENET_DMA_INTEN_NIE
 #endif
@@ -1477,6 +1469,15 @@ static void vClearTXBuffers()
 	#define ETH_MEDIA_INTERFACE_RMII ARM_ETH_INTERFACE_RMII
 #endif
 
+
+HAL_StatusTypeDef HAL_ETH_Init( ETH_HandleTypeDef* pxETH )
+{
+	HAL_StatusTypeDef xResult = ARM_DRIVER_ERROR;	
+	if (SUCCESS == enet_init( pxETH->Init.AutoNegotiation /*ENET_AUTO_NEGOTIATION*/, pxETH->Init.ChecksumMode /* ENET_AUTOCHECKSUM_DROP_FAILFRAMES*/, pxETH->Init.RxMode /* ENET_RECEIVEALL*/))
+	 xResult = ARM_DRIVER_OK;
+	return xResult;
+}
+
 BaseType_t xNetworkInterfaceInitialise( void )
 {
     HAL_StatusTypeDef hal_eth_init_status;
@@ -1597,6 +1598,7 @@ BaseType_t xNetworkInterfaceInitialise( void )
         if( xPhyObject.ulLinkStatusMask != 0U )
         {
             xETH.Instance->DMAIER |= ETH_DMA_ALL_INTS;
+						ENET_DMA_INTEN |= ETH_DMA_ALL_INTS; 
             xResult = pdPASS;
             FreeRTOS_printf( ( "Link Status is high\n" ) );
         }
@@ -1613,8 +1615,17 @@ BaseType_t xNetworkInterfaceInitialise( void )
     return xResult;
 }
 /*-----------------------------------------------------------*/
+#warning Check ETH_DMATXDESC_TCH/ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL/ETH_CHECKSUM_BY_HARDWARE
 #ifndef ETH_DMATXDESC_TCH
-#define ETH_DMATXDESC_TCH ENET_TDES0_TCHM
+	#define ETH_DMATXDESC_TCH ENET_TDES0_TCHM 
+#endif
+
+#ifndef ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL
+	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ENET_TDES0_CM
+#endif
+
+#ifndef	ETH_CHECKSUM_BY_HARDWARE
+	#define ETH_CHECKSUM_BY_HARDWARE 1
 #endif
 static void prvDMATxDescListInit()
 {
@@ -1665,7 +1676,12 @@ static void prvDMATxDescListInit()
 }
 /*-----------------------------------------------------------*/
 #ifndef ETH_DMARXDESC_RCH
-#define ETH_DMARXDESC_RCH ENET_RDES1_RCHM
+	#define ETH_DMARXDESC_RCH ENET_RDES1_RCHM
+#endif
+
+#ifndef ETH_DMARXDESC_OWN	
+	#define ETH_DMARXDESC_OWN ENET_RDES0_DAV
+	#warning Check of ETH_DMARXDESC_OWN bit is equal to ENET_RDES0_DAV bit
 #endif
 static void prvDMARxDescListInit()
 {
@@ -1752,7 +1768,26 @@ static void prvDMARxDescListInit()
     }
 #endif /* if ( ipconfigUSE_LLMNR != 0 ) || ( ipconfigUSE_MDNS != 0 ) */
 /*-----------------------------------------------------------*/
+#warning Check define ETH_DMATXDESC_CIC / ETH_DMATXDESC_IC / ETH_DMATXDESC_FS / ETH_DMATXDESC_LS / ETH_DMATXDESC_TBS1
+#ifndef ETH_DMATXDESC_CIC
+	#define ETH_DMATXDESC_CIC ENET_TDES0_INTC
+#endif
 
+#ifndef ETH_DMATXDESC_IC
+	#define ETH_DMATXDESC_IC ENET_TDES0_INTC
+#endif
+
+#ifndef ETH_DMATXDESC_FS
+	#define ETH_DMATXDESC_FS ENET_TDES0_FSG
+#endif	
+
+#ifndef ETH_DMATXDESC_LS
+	#define ETH_DMATXDESC_LS ENET_TDES0_LSG
+#endif
+
+#ifndef ETH_DMATXDESC_TBS1
+	#define ETH_DMATXDESC_TBS1	ENET_TDES1_TB1S
+#endif	
 BaseType_t xNetworkInterfaceOutput( NetworkBufferDescriptor_t * const pxDescriptor,
                                     BaseType_t bReleaseAfterSend )
 {
@@ -2008,8 +2043,29 @@ static void prvPassEthMessages( NetworkBufferDescriptor_t * pxDescriptor )
 
 #ifndef ETH_DMARXDESC_OWN
 	#define ETH_DMARXDESC_OWN ENET_RDES0_DAV
-	#warning Check of ETH_DMARXDESC_OWN bit is equal to ENET_RDES0_DAV bit
+	#warning Check the ETH_DMARXDESC_OWN bit is equal to ENET_RDES0_DAV bit
 #endif
+
+#warning Check define ETH_DMARXDESC_FL / ETH_DMARXDESC_CE / ETH_DMARXDESC_IPV4HCE / ETH_DMARXDESC_FT / ETH_DMASR_RBUS
+#ifndef ETH_DMARXDESC_FL
+	#define ETH_DMARXDESC_FL			ENET_RDES0_FRML
+#endif
+
+#ifndef ETH_DMARXDESC_CE
+	#define ETH_DMARXDESC_CE 			ENET_RDES0_CERR
+#endif
+
+#ifndef ETH_DMARXDESC_IPV4HCE
+	#define ETH_DMARXDESC_IPV4HCE ENET_RDES0_IPHERR
+#endif
+
+#ifndef ETH_DMARXDESC_FT
+	#define ETH_DMARXDESC_FT 			ENET_RDES0_FRMT
+#endif
+
+#ifndef ETH_DMASR_RBUS
+	#define ETH_DMASR_RBUS	ENET_DMA_STAT_RBU
+#endif	
 static BaseType_t prvNetworkInterfaceInput( void )
 {
     #if ( ipconfigUSE_LINKED_RX_MESSAGES != 0 )
@@ -2030,8 +2086,7 @@ static BaseType_t prvNetworkInterfaceInput( void )
         BaseType_t xAccepted = pdTRUE;
 
         /* Get the Frame Length of the received packet: subtract 4 bytes of the CRC */
-        xReceivedLength = ( ( pxDMARxDescriptor->Status & ETH_DMARXDESC_FL ) >> ETH_DMARXDESC_FRAMELENGTHSHIFT ) - 4;
+        xReceivedLength = enet_rxframe_size_get(); //xReceivedLength = ( ( pxDMARxDescriptor->Status & ETH_DMARXDESC_FL ) >> ETH_DMARXDESC_FRAMELENGTHSHIFT ) - 4;
-
         pucBuffer = ( uint8_t * ) pxDMARxDescriptor->Buffer1Addr;
 
         /* Update the ETHERNET DMA global Rx descriptor with next Rx descriptor */
@@ -2165,6 +2220,21 @@ static BaseType_t prvNetworkInterfaceInput( void )
     return( xReceivedLength > 0 );
 }
 /*-----------------------------------------------------------*/
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister( ETH_HandleTypeDef* pxETH, uint16_t xRegister, uint32_t* pulValue ) 
+{
+	if((pxETH->Init.PhyAddress >= 0) & (xRegister >= 0x00) & pulValue > 0x0000)
+	{
+		if(SUCCESS == enet_phy_write_read(ENET_PHY_READ, pxETH->Init.PhyAddress, xRegister, (uint16_t*)pulValue))
+			return ARM_DRIVER_OK;
+		else
+		{
+			FreeRTOS_debug_printf(("HAL_ETH_ReadPHYRegister_ERROR\n"));		
+			return ARM_DRIVER_ERROR;
+		}
+	}else
+		FreeRTOS_debug_printf(("HAL_ETH_ReadPHYRegister_ERROR_PARAMETER\n"));		
+		return ARM_DRIVER_ERROR_PARAMETER;
+}
 
 
 BaseType_t xSTM32_PhyRead( BaseType_t xAddress,
@@ -2191,6 +2261,21 @@ BaseType_t xSTM32_PhyRead( BaseType_t xAddress,
     return xResult;
 }
 /*-----------------------------------------------------------*/
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister( ETH_HandleTypeDef* pxETH, uint16_t xRegister, uint32_t ulValue)
+{
+	if((pxETH->Init.PhyAddress >= 0) & (xRegister >= 0x00) & ulValue >= 0x0000)
+	{
+		if(SUCCESS == enet_phy_write_read(ENET_PHY_WRITE, pxETH->Init.PhyAddress, xRegister, (uint16_t*)(&ulValue)))
+			return ARM_DRIVER_OK;
+		else
+		{
+			FreeRTOS_debug_printf(("HAL_ETH_WritePHYRegister_ERROR\n"));		
+			return ARM_DRIVER_ERROR;
+		}
+	}else
+		FreeRTOS_debug_printf(("HAL_ETH_WritePHYRegister_ERROR_PARAMETER\n"));		
+		return ARM_DRIVER_ERROR_PARAMETER;
+}
 
 BaseType_t xSTM32_PhyWrite( BaseType_t xAddress,
                             BaseType_t xRegister,
@@ -2223,18 +2308,88 @@ void vMACBProbePhy( void )
     xPhyDiscover( &xPhyObject );
     xPhyConfigure( &xPhyObject, &xPHYProperties );
 }
+
+uint32_t HAL_ETH_ConfigMAC( ETH_HandleTypeDef* pxETH, ETH_MACInitTypeDef* pxMACInit )
+{
+	ErrStatus xResult = ARM_DRIVER_ERROR;	
+	if (SUCCESS == enet_init( pxETH->Init.AutoNegotiation /*ENET_AUTO_NEGOTIATION*/, pxETH->Init.ChecksumMode /* ENET_AUTOCHECKSUM_DROP_FAILFRAMES*/, pxETH->Init.RxMode /* ENET_RECEIVEALL*/))
+	 xResult = ARM_DRIVER_OK;
+	
+//	enet_interrupt_enable( ENET_DMA_INT_RIE );	
+//#ifdef DEBUG_TI_IRQ	
+//	enet_interrupt_enable( ENET_DMA_INT_TIE );
+//#elif defined DEBUG_TBU_IRQ	
+//	enet_interrupt_enable( ENET_DMA_INT_TBUIE );
+//#elif defined DEBUG_ER_IRQ		
+//  enet_interrupt_enable( ENET_DMA_INT_ERIE );
+//#endif	
+//	
+//	enet_interrupt_enable( ENET_DMA_INT_NIE );
+//	
+//#ifdef DEBUG_TJT_IRQ
+//  enet_interrupt_enable( ENET_DMA_INT_TJTIE );
+//#elif defined DEBUG_TPS_IRQ	
+//  enet_interrupt_enable( ENET_DMA_INT_TPSIE );
+//#elif defined DEBUG_TU_IRQ	
+//  enet_interrupt_enable( ENET_DMA_INT_TUIE );
+//#elif defined DEBUG_RBU_IRQ		
+//	enet_interrupt_enable( ENET_DMA_INT_RBUIE );
+//#elif defined DEBUG_RPS_IRQ		
+//  enet_interrupt_enable( ENET_DMA_INT_RPSIE );
+//#elif defined DEBUG_RO_IRQ		
+//	enet_interrupt_enable( ENET_DMA_INT_ROIE );
+//#elif defined DEBUG_RWT_IRQ			
+//  enet_interrupt_enable( ENET_DMA_INT_RWTIE );
+//#elif defined DEBUG_ET_IRQ			
+//  enet_interrupt_enable( ENET_DMA_INT_ETIE );
+//#elif defined DEBUG_FBE_IRQ			
+//  enet_interrupt_enable( ENET_DMA_INT_FBEIE );
+//#endif	
+//#if defined ( DEBUG_TJT_IRQ ) || \
+//	  defined ( DEBUG_TPS_IRQ ) || \
+//		defined ( DEBUG_TU_IRQ  ) || \
+//		defined ( DEBUG_RBU_IRQ ) || \
+//		defined ( DEBUG_RPS_IRQ ) || \
+//		defined ( DEBUG_RO_IRQ  ) || \
+//		defined ( DEBUG_RWT_IRQ ) || \
+//		defined ( DEBUG_ET_IRQ  ) || \
+//		defined ( DEBUG_FBE_IRQ )
+//	enet_interrupt_enable( ENET_DMA_INT_AIE );	
+//#endif
+
+	return xResult;
+}
+
+void HAL_ETH_Start( ETH_HandleTypeDef* pxETH )
+{
+	enet_enable();
+}
+
+void HAL_ETH_Stop( ETH_HandleTypeDef* pxETH )
+{
+	enet_disable();
+	enet_deinit();
+}
 /*-----------------------------------------------------------*/
 
+#ifndef IS_ETH_SPEED 
+	#define IS_ETH_SPEED(speed) (speed == ETH_SPEED_10M | speed == ETH_SPEED_100M)
+#endif
+
+#ifndef IS_ETH_DUPLEX_MODE 
+	#define IS_ETH_DUPLEX_MODE(mode) (mode == ETH_MODE_FULLDUPLEX | mode == ETH_MODE_HALFDUPLEX)
+#endif
+
 static void prvEthernetUpdateConfig( BaseType_t xForce )
 {
-    FreeRTOS_printf( ( "prvEthernetUpdateConfig: LS mask %02lX Force %d\n",
+    FreeRTOS_printf( ( "prvEthernetUpdateConfig: LS mask 0x%02X Force %d\n",
                        xPhyObject.ulLinkStatusMask,
                        ( int ) xForce ) );
 
     if( ( xForce != pdFALSE ) || ( xPhyObject.ulLinkStatusMask != 0 ) )
     {
         /* Restart the auto-negotiation. */
-        if( xETH.Init.AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE )
+        if( xETH.Init.AutoNegotiation == ETH_AUTONEGOTIATION_ENABLE )
         {
             xPhyStartAutoNegotiation( &xPhyObject, xPhyGetMask( &xPhyObject ) );
 
@@ -2263,8 +2418,8 @@ static void prvEthernetUpdateConfig( BaseType_t xForce )
         else /* AutoNegotiation Disable */
         {
             /* Check parameters */
-            assert_param( IS_ETH_SPEED( xETH.Init.Speed ) );
+            configASSERT( IS_ETH_SPEED( xETH.Init.Speed ) );
-            assert_param( IS_ETH_DUPLEX_MODE( xETH.Init.DuplexMode ) );
+            configASSERT( IS_ETH_DUPLEX_MODE( xETH.Init.DuplexMode ) );
 
             if( xETH.Init.DuplexMode == ETH_MODE_FULLDUPLEX )
             {
@@ -2291,7 +2446,7 @@ static void prvEthernetUpdateConfig( BaseType_t xForce )
         }
 
         /* ETHERNET MAC Re-Configuration */
-        HAL_ETH_ConfigMAC( &xETH, ( ETH_MACInitTypeDef * ) NULL );
+        HAL_ETH_ConfigMAC( &xETH, ( ETH_MACInitTypeDef * ) NULL/*xMacInitStatus*/ );
 
         /* Restart MAC interface */
         HAL_ETH_Start( &xETH );
@@ -2409,11 +2564,55 @@ static void prvEMACHandlerTask( void * pvParameters )
     }
 }
 /*-----------------------------------------------------------*/
+/**
+  \fn          void ENET_IRQHandler(void)
+  \brief       Ethernet IRQ Handler 
+*/
+void ENET_IRQHandler(void)
+{
+	portBASE_TYPE xHigherPriorityTaskWoken  = pdFALSE;
+	
+	if (SET == enet_interrupt_flag_get( ENET_DMA_INT_FLAG_RS ))
+	{
+		enet_interrupt_flag_clear( ENET_DMA_INT_FLAG_RS_CLR );
+		HAL_ETH_RxCpltCallback( &xETH );
+	}
+	else if (SET == enet_interrupt_flag_get( ENET_DMA_INT_FLAG_TS ))
+	{
+		enet_interrupt_flag_clear( ENET_DMA_INT_FLAG_RS_CLR );
+		HAL_ETH_TxCpltCallback( &xETH );
+	}
+	else
+	{
+		portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+	}
 
-void ETH_IRQHandler( void )
+#ifdef DEBUG_RBU_IRQ
+	if (SET == enet_interrupt_flag_get(ENET_DMA_INT_FLAG_RBU))
+	{
+		enet_interrupt_flag_clear(ENET_DMA_INT_FLAG_RBU_CLR);		
+		vTaskNotifyGiveIndexedFromISR(vTaskToggleLed_Handle, 0, &pxHigherPriorityTaskWoken );
+	}
+#elif defined (DEBUG_TBU_IRQ)
+	if (SET == enet_interrupt_flag_get(ENET_DMA_INT_FLAG_TBU))
+	{
+		enet_interrupt_flag_clear(ENET_DMA_INT_FLAG_TBU_CLR);		
+		vTaskNotifyGiveFromISR(vTaskHelloWorld_Handle, &pxHigherPriorityTaskWoken );
+	}
+#elif defined (DEBUG_RBU_IRQ)	
+	if (SET == enet_interrupt_flag_get(ENET_DMA_INT_FLAG_ET))
+	{
+		enet_interrupt_flag_clear(ENET_DMA_INT_FLAG_ET_CLR);		
+		vTaskNotifyGiveIndexedFromISR(vTaskHelloWorld_Handle, 1, &pxHigherPriorityTaskWoken );
+	}
+#endif	
+	//portYIELD_FROM_ISR( xHigherPriorityTaskWoken );	
+}
+/*void ETH_IRQHandler( void )
 {
     HAL_ETH_IRQHandler( &xETH );
-}
+}*/
+
 /*
  * Some constants, hardware definitions and comments taken from ST's HAL driver
  * library, COPYRIGHT(c) 2015 STMicroelectronics.

RTE/Device/GD32F107VC/startup_gd32f10x_cl.s

@@ -40,7 +40,7 @@
 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 
-Stack_Size          EQU     0x00000200
+Stack_Size          EQU     0x00001200
 
                     AREA    STACK, NOINIT, READWRITE, ALIGN = 3
 Stack_Mem           SPACE   Stack_Size

RTE/RTOS/FreeRTOSConfig.h

@@ -50,7 +50,11 @@ extern uint32_t SystemCoreClock;
 /* Constants that describe the hardware and memory usage. */
 #define configCPU_CLOCK_HZ                    (SystemCoreClock)
 #define configTICK_RATE_HZ                    ((TickType_t)1000)
-#define configTOTAL_HEAP_SIZE                 ((size_t)40*1024)
+#ifndef STM32_PORT
+	#define configTOTAL_HEAP_SIZE                 ((size_t)40*1024)
+#else
+	#define configTOTAL_HEAP_SIZE                 ((size_t)40*1024)
+#endif
 #define configMINIMAL_STACK_SIZE              ((uint16_t)256)
 #define configSUPPORT_DYNAMIC_ALLOCATION      1
 #define configSUPPORT_STATIC_ALLOCATION       0

Test_project_for_GD32107C-EVAL.uvoptx

@@ -153,7 +153,24 @@
           <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL040000 -FP0($$Device:GD32F107VC$Flash\GD32F10x_CL.FLM))</Name>
         </SetRegEntry>
       </TargetDriverDllRegistry>
-      <Breakpoint/>
+      <Breakpoint>
+        <Bp>
+          <Number>0</Number>
+          <Type>0</Type>
+          <LineNumber>323</LineNumber>
+          <EnabledFlag>1</EnabledFlag>
+          <Address>0</Address>
+          <ByteObject>0</ByteObject>
+          <HtxType>0</HtxType>
+          <ManyObjects>0</ManyObjects>
+          <SizeOfObject>0</SizeOfObject>
+          <BreakByAccess>0</BreakByAccess>
+          <BreakIfRCount>0</BreakIfRCount>
+          <Filename>.\FreeRTOS\source\FreeRTOS_IP.c</Filename>
+          <ExecCommand></ExecCommand>
+          <Expression></Expression>
+        </Bp>
+      </Breakpoint>
       <WatchWindow1>
         <Ww>
           <count>0</count>
@@ -401,18 +418,6 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>.\PHY\PHY_DP83848C.c</PathWithFileName>
-      <FilenameWithoutPath>PHY_DP83848C.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>1</GroupNumber>
-      <FileNumber>6</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
       <PathWithFileName>.\rf_switch_driver.c</PathWithFileName>
       <FilenameWithoutPath>rf_switch_driver.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
@@ -420,7 +425,7 @@
     </File>
     <File>
       <GroupNumber>1</GroupNumber>
-      <FileNumber>7</FileNumber>
+      <FileNumber>6</FileNumber>
       <FileType>5</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -430,6 +435,18 @@
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>7</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\PHY\PHY_DP83848C.c</PathWithFileName>
+      <FilenameWithoutPath>PHY_DP83848C.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
   </Group>
 
   <Group>

Test_project_for_GD32107C-EVAL.uvprojx

@@ -315,7 +315,7 @@
           </ArmAdsMisc>
           <Cads>
             <interw>1</interw>
-            <Optim>1</Optim>
+            <Optim>0</Optim>
             <oTime>0</oTime>
             <SplitLS>0</SplitLS>
             <OneElfS>0</OneElfS>
@@ -338,7 +338,7 @@
             <v6WtE>0</v6WtE>
             <v6Rtti>0</v6Rtti>
             <VariousControls>
-              <MiscControls>-D DEBUG -Wno-pragma-pack -Wno-macro-redefined -U CENTRALISED_DEFERRED_IRQ_HADLING</MiscControls>
+              <MiscControls>-D DEBUG -D STM32_PORT -Wno-pragma-pack -Wno-macro-redefined -U CENTRALISED_DEFERRED_IRQ_HADLING</MiscControls>
               <Define>DEBUG_LISTEN_SOCK</Define>
               <Undefine></Undefine>
               <IncludePath>.\FreeRTOS\source\portable\NetworkInterface\include;.\FreeRTOS\source\include;.\FreeRTOS\source\portable\Compiler\Keil;.\DemoTasks\include;..\GigaDevice_test;.\include;.\PHY</IncludePath>
@@ -405,11 +405,6 @@
               <FileType>1</FileType>
               <FilePath>.\DemoTasks\TCPEchoClient_SingleTasks.c</FilePath>
             </File>
-            <File>
-              <FileName>PHY_DP83848C.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\PHY\PHY_DP83848C.c</FilePath>
-            </File>
             <File>
               <FileName>rf_switch_driver.c</FileName>
               <FileType>1</FileType>
@@ -420,6 +415,11 @@
               <FileType>5</FileType>
               <FilePath>.\FreeRTOS\source\include\IPTraceMacro.h</FilePath>
             </File>
+            <File>
+              <FileName>PHY_DP83848C.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\PHY\PHY_DP83848C.c</FilePath>
+            </File>
           </Files>
         </Group>
         <Group>

main.c

@@ -276,9 +276,11 @@ static void vInitMCU(void)
 	gpio_init(RMII_CRS_DV_PORT, 	GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, RMII_CRS_DV);	
 	
 	/* Enable Ethernet MAC */
+#ifndef STM32_PORT	
 	enet_descriptors_chain_init(ENET_DMA_TX);
 	enet_descriptors_chain_init(ENET_DMA_RX);
 	enet_enable();
+#endif	
 	//nvic_irq_enable(ENET_IRQn, ipconfigMAC_INTERRUPT_PRIORITY, 0xFF);
 	__disable_irq();
 	NVIC_ClearPendingIRQ(ENET_IRQn);