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Modified NetworkInterface.c

This commit is contained in:
Alexei 2023-04-14 01:39:48 +07:00
parent 585e8dc35d
commit 7d5504b4b5
3 changed files with 86 additions and 20 deletions
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2
FreeRTOS/source/include/FreeRTOSIPConfig.h
View File

@ -38,7 +38,7 @@
/* It is not sensible for this macro to have a default value as it is hardware
* dependent. */
#define ipconfigBYTE_ORDER pdFREERTOS_LITTLE_ENDIAN
//#define ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS 4
#define ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS 45
#define ipconfigUSE_NETWORK_EVENT_HOOK 1
#define ipconfigUSE_DHCP 1
#define ipconfigUSE_DHCP_HOOK 1

5
FreeRTOS/source/include/NetworkInterface.h
View File

@ -43,6 +43,10 @@
BaseType_t xNetworkInterfaceInitialise( void );
BaseType_t xNetworkInterfaceOutput( NetworkBufferDescriptor_t * const pxDescriptor,BaseType_t xReleaseAfterSend );
#else /*STM32_PORT*/
#include "stdint.h"
#include "FreeRTOS.h"
#include "FreeRTOS_IP.h"
#include "FreeRTOSIPConfig.h"
/* *INDENT-ON* */
/**
@ -301,6 +305,7 @@ typedef struct
} ETH_DMARxFrameInfos;
#define ETH_TypeDef void
typedef uint8_t HAL_LockTypeDef;
/**
* @brief ETH Handle Structure definition
*/

99
FreeRTOS/source/portable/NetworkInterface/board_family/NetworkInterface.c
View File

@ -1053,8 +1053,8 @@ void PendedReceiveHandler( void *pvParameter1, uint32_t ulParameter2 )
//#include "stm32fxx_hal_eth.h"
/*#include "Driver_ETH.h"
#include "Driver_ETH_MAC.h"
#include "Driver_ETH.h"
/*#include "Driver_ETH_MAC.h"
#include "Driver_ETH_PHY.h"*/
/* If ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES is set to 1, then the Ethernet
* driver will filter incoming packets and only pass the stack those packets it
@ -1115,12 +1115,31 @@ BaseType_t xGetPhyLinkStatus( void )
/* Calculate the maximum packet size that the DMA can receive. */
#define EMAC_DMA_BUFFER_SIZE ( ( uint32_t ) ( ETH_MAX_PACKET_SIZE - ipBUFFER_PADDING ) )
#define ETH_DMA_IT_T ENET_DMA_INTEN_TIE /*!< transmit interrupt enable */
#define ETH_DMA_IT_TPS ENET_DMA_INTEN_TPSIE /*!< transmit process stopped interrupt enable */
#warning Check define ETH_DMA_IT_MMC ENET_DMA_INTEN_TBUIE
#define ETH_DMA_IT_MMC ENET_DMA_INTEN_TBUIE /*!< transmit buffer unavailable interrupt enable */
#define ETH_DMA_IT_TJT ENET_DMA_INTEN_TJTIE /*!< transmit jabber timeout interrupt enable */
#define ETH_DMA_IT_RO ENET_DMA_INTEN_ROIE /*!< receive overflow interrupt enable */
#define ETH_DMA_IT_TU ENET_DMA_INTEN_TUIE /*!< transmit underflow interrupt enable */
#define ETH_DMA_IT_R ENET_DMA_INTEN_RIE /*!< receive interrupt enable */
#define ETH_DMA_IT_RBU ENET_DMA_INTEN_RBUIE /*!< receive buffer unavailable interrupt enable */
#define ETH_DMA_IT_RPS ENET_DMA_INTEN_RPSIE /*!< receive process stopped interrupt enable */
#define ETH_DMA_IT_RWT ENET_DMA_INTEN_RWTIE /*!< receive watchdog timeout interrupt enable */
#warning Check define ETH_DMA_IT_PMT ENET_DMA_INTEN_ETIE /*!< early transmit interrupt enable */
#define ETH_DMA_IT_PMT ENET_DMA_INTEN_ETIE /*!< early transmit interrupt enable */
#define ETH_DMA_IT_FBE ENET_DMA_INTEN_FBEIE /*!< fatal bus error interrupt enable */
#define ETH_DMA_IT_ER ENET_DMA_INTEN_ERIE /*!< early receive interrupt enable */
#define ETH_DMA_IT_AIS ENET_DMA_INTEN_AIE /*!< abnormal interrupt summary enable */
#define ETH_DMA_IT_NIS ENET_DMA_INTEN_NIE /*!< normal interrupt summary enable */
#warning Check ETH_DMA_IT_TST
#define ETH_DMA_ALL_INTS \
( ETH_DMA_IT_TST | ETH_DMA_IT_PMT | ETH_DMA_IT_MMC | ETH_DMA_IT_NIS | \
( /*ETH_DMA_IT_TST |*/ ETH_DMA_IT_PMT | ETH_DMA_IT_MMC | ETH_DMA_IT_NIS | \
ETH_DMA_IT_AIS | ETH_DMA_IT_ER | ETH_DMA_IT_FBE | ETH_DMA_IT_RWT | \
ETH_DMA_IT_RPS | ETH_DMA_IT_RBU | ETH_DMA_IT_R | ETH_DMA_IT_TU | \
ETH_DMA_IT_RO | ETH_DMA_IT_TJT | ETH_DMA_IT_TPS | ETH_DMA_IT_T )
#ifndef NETWORK_BUFFER_HEADER_SIZE
#define NETWORK_BUFFER_HEADER_SIZE ( ipBUFFER_PADDING )
#endif
@ -1277,33 +1296,39 @@ static SemaphoreHandle_t xTXDescriptorSemaphore = NULL;
*/
/* MAC buffers: ---------------------------------------------------------*/
/* Put the DMA descriptors in '.first_data'.
* This is important for STM32F7, which has an L1 data cache.
* The first 64KB of the SRAM is not cached.
* See README.TXT in this folder. */
/* Ethernet Rx MA Descriptor */
__attribute__( ( aligned( 32 ) ) )
#if defined( STM32F7xx )
__attribute__( ( section( ".first_data" ) ) )
#ifndef ETH_RXBUFNB
#define ETH_RXBUFNB ENET_RXBUF_NUM
#endif
#ifndef ETH_RX_BUF_SIZE
#define ETH_RX_BUF_SIZE ENET_RXBUF_SIZE
#endif
__attribute__( ( aligned( 32 ) ) )
ETH_DMADescTypeDef DMARxDscrTab[ ETH_RXBUFNB ];
#if ( ipconfigZERO_COPY_RX_DRIVER == 0 )
/* Ethernet Receive Buffer */
__ALIGN_BEGIN uint8_t Rx_Buff[ ETH_RXBUFNB ][ ETH_RX_BUF_SIZE ] __ALIGN_END;
uint8_t Rx_Buff[ ETH_RXBUFNB ][ ETH_RX_BUF_SIZE ] __attribute__ ((aligned (4)));
#endif
/* Ethernet Tx DMA Descriptor */
__attribute__( ( aligned( 32 ) ) )
#if defined( STM32F7xx )
__attribute__( ( section( ".first_data" ) ) )
#ifndef ETH_TXBUFNB
#define ETH_TXBUFNB ENET_TXBUF_NUM
#endif
#ifndef ETH_TX_BUF_SIZE
#define ETH_TX_BUF_SIZE ENET_TXBUF_SIZE
#endif
__attribute__( ( aligned( 32 ) ) )
ETH_DMADescTypeDef DMATxDscrTab[ ETH_TXBUFNB ];
#if ( ipconfigZERO_COPY_TX_DRIVER == 0 )
/* Ethernet Transmit Buffer */
__ALIGN_BEGIN uint8_t Tx_Buff[ ETH_TXBUFNB ][ ETH_TX_BUF_SIZE ] __ALIGN_END;
uint8_t Tx_Buff[ ETH_TXBUFNB ][ ETH_TX_BUF_SIZE ] __attribute__ ((aligned (4)));
#endif
/* DMATxDescToClear points to the next TX DMA descriptor
@ -1375,7 +1400,10 @@ void HAL_ETH_TxCpltCallback( ETH_HandleTypeDef * heth )
}
}
/*-----------------------------------------------------------*/
#ifndef ETH_DMATXDESC_OWN
#define ETH_DMATXDESC_OWN ENET_TDES0_DAV
#warning Check of ETH_DMATXDESC_OWN bit is equal to ENET_TDES0_DAV bit
#endif
static void vClearTXBuffers()
{
__IO ETH_DMADescTypeDef * txLastDescriptor = xETH.TxDesc;
@ -1423,6 +1451,31 @@ static void vClearTXBuffers()
}
}
/*-----------------------------------------------------------*/
#warning Check HAL_StatusTypeDef/ETH/ETH_AUTONEGOTIATION_ENABLE/ETH_SPEED_100M/ETH_MODE_FULLDUPLEX/ETH_RXINTERRUPT_MODE/ETH_CHECKSUM_BY_SOFTWARE/ETH_MEDIA_INTERFACE_RMII
#define HAL_StatusTypeDef bool
#define ETH (void*)ENET
#ifndef ETH_AUTONEGOTIATION_ENABLE
#define ETH_AUTONEGOTIATION_ENABLE ENET_AUTO_NEGOTIATION
#endif
#ifndef ETH_SPEED_100M
#define ETH_SPEED_100M ENET_100M_FULLDUPLEX
#endif
#ifndef ETH_MODE_FULLDUPLEX
#define ETH_MODE_FULLDUPLEX ENET_100M_FULLDUPLEX
#endif
#ifndef ETH_RXINTERRUPT_MODE
#define ETH_RXINTERRUPT_MODE ENET_DMA_INTEN_RIE|ENET_DMA_INTEN_NIE
#endif
#ifndef ETH_CHECKSUM_BY_SOFTWARE
#define ETH_CHECKSUM_BY_SOFTWARE 1
#endif
#ifndef ETH_MEDIA_INTERFACE_RMII
#define ETH_MEDIA_INTERFACE_RMII ARM_ETH_INTERFACE_RMII
#endif
BaseType_t xNetworkInterfaceInitialise( void )
{
@ -1445,7 +1498,7 @@ BaseType_t xNetworkInterfaceInitialise( void )
{
/* Initialise ETH */
xETH.Instance = ETH;
xETH.Instance = ETH;
xETH.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
xETH.Init.Speed = ETH_SPEED_100M;
xETH.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
@ -1560,7 +1613,9 @@ BaseType_t xNetworkInterfaceInitialise( void )
return xResult;
}
/*-----------------------------------------------------------*/
#ifndef ETH_DMATXDESC_TCH
#define ETH_DMATXDESC_TCH ENET_TDES0_TCHM
#endif
static void prvDMATxDescListInit()
{
ETH_DMADescTypeDef * pxDMADescriptor;
@ -1609,7 +1664,9 @@ static void prvDMATxDescListInit()
xETH.Instance->DMATDLAR = ( uint32_t ) DMATxDscrTab;
}
/*-----------------------------------------------------------*/
#ifndef ETH_DMARXDESC_RCH
#define ETH_DMARXDESC_RCH ENET_RDES1_RCHM
#endif
static void prvDMARxDescListInit()
{
ETH_DMADescTypeDef * pxDMADescriptor;
@ -1949,6 +2006,10 @@ static void prvPassEthMessages( NetworkBufferDescriptor_t * pxDescriptor )
}
}
#ifndef ETH_DMARXDESC_OWN
#define ETH_DMARXDESC_OWN ENET_RDES0_DAV
#warning Check of ETH_DMARXDESC_OWN bit is equal to ENET_RDES0_DAV bit
#endif
static BaseType_t prvNetworkInterfaceInput( void )
{
#if ( ipconfigUSE_LINKED_RX_MESSAGES != 0 )