54 lines
1.8 KiB
VHDL
54 lines
1.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package sim_switcher_pkg is
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type arr_modnum_t is array (natural range <>) of natural range 0 to 15;
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component sim_mux is
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port (
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reg_sim_modemnum : arr_modnum_t(0 to 7);
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sim_rst_o : out std_logic_vector(7 downto 0);
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mod_simrst_i : in std_logic_vector(7 downto 0);
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sim_clk_o : out std_logic_vector(7 downto 0);
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mod_clk_i : in std_logic_vector(7 downto 0);
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mod_detect_o : out std_logic_vector(3 downto 0);
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sim_detect_i : in std_logic_vector(7 downto 0);
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sw_mod_data_i : out std_logic_vector(7 downto 0); -- For switched tri-state buffer there are input and output part of
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mod_data_i : in std_logic_vector(7 downto 0); -- the lines which are switched transparently, thus ports
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mod_data_o : out std_logic_vector(7 downto 0); -- sw_mod_data_i is actual output and sw_mod_data_o is
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sw_mod_data_o : in std_logic_vector(7 downto 0) -- actual input. Please, don't be confused.
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);
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end component sim_mux;
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component i2c_slave is
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generic (
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SLAVE_ADDR : std_logic_vector(6 downto 0)
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);
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port (
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scl : inout std_logic;
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sda : inout std_logic;
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clk : in std_logic;
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rst : in std_logic;
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-- User interface
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read_req : out std_logic;
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data_to_master : in std_logic_vector(7 downto 0);
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data_valid : out std_logic;
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data_from_master : out std_logic_vector(7 downto 0)
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);
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end component i2c_slave;
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component odio_repeater is
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generic (
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WAIT_CYCLES : integer := 3
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);
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port (
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clk : in std_logic;
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rstn : in std_logic;
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signal_n1 : inout std_logic;
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signal_n2 : inout std_logic
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);
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end component odio_repeater;
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end package sim_switcher_pkg; |