64 lines
2.0 KiB
VHDL
64 lines
2.0 KiB
VHDL
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-- File : debounce.vhd
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------------------------------------------------------------
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-- Author : Peter Samarin <peter.samarin@gmail.com>
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------------------------------------------------------------
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-- Copyright (c) 2016 Peter Samarin
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------------------------------------------------------------
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-- Description: debouncing circuit that forwards only
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-- signals that have been stable for the whole duration of
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-- the counter
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------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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------------------------------------------------------------
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entity debounce is
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generic (
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WAIT_CYCLES : integer := 5);
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port (
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signal_in : in std_logic;
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signal_out : out std_logic;
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clk : in std_logic);
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end entity debounce;
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------------------------------------------------------------
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architecture arch of debounce is
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type state_t is (idle, check_input_stable);
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signal state_reg : state_t := idle;
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signal out_reg : std_logic := signal_in;
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signal signal_in_reg : std_logic;
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signal counter : integer range 0 to WAIT_CYCLES-1 := 0;
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begin
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process (clk) is
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begin
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if rising_edge(clk) then
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case state_reg is
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when idle =>
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if out_reg /= signal_in then
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signal_in_reg <= signal_in;
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state_reg <= check_input_stable;
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counter <= WAIT_CYCLES-1;
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end if;
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when check_input_stable =>
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if counter = 0 then
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if signal_in = signal_in_reg then
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out_reg <= signal_in;
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end if;
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state_reg <= idle;
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else
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if signal_in /= signal_in_reg then
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state_reg <= idle;
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end if;
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counter <= counter - 1;
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end if;
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end case;
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end if;
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end process;
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-- output
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signal_out <= to_UX01(out_reg);
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end architecture arch;
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