.gitignore

@@ -1 +0,0 @@
-*.bak

sim_switcher_pkg.vhd

@@ -60,4 +60,30 @@ package sim_switcher_pkg is
 		);
 	end component i2c_slave;
 
+	component i2c_repeater is
+	generic (
+		WAIT_CYCLES : integer := 3
+	);
+	port (
+		clk       : in    std_logic;
+		rstn      : in    std_logic;
+		pr_scl    : inout std_logic;
+		pr_sda    : inout std_logic;
+		sec_scl   : inout std_logic;
+		sec_sda   : inout std_logic
+	);
+	end component i2c_repeater;
+
+	component odio_repeater is
+	generic (
+		WAIT_CYCLES : integer := 3
+	);
+	port (
+		clk       : in    std_logic;
+		rstn      : in    std_logic;
+		signal_n1 : inout std_logic;
+		signal_n2 : inout std_logic
+	);
+	end component odio_repeater;
+
 end package sim_switcher_pkg;

sim_switcher_top.vhd

@@ -8,10 +8,10 @@ use work.sim_switcher_pkg.all;
 entity sim_switcher_top is
     generic (
 		-- General parameters
-		SYSFREQ       	: integer := 25_000_000;						-- System clock frequency
+		SYSFREQ       	: integer := 25_000_000;				-- System clock frequency
-		INSIM						: std_logic := '0';  				-- In Simulation flag: 0 - real work (default), 1 - simulation
+		INSIM						: std_logic := '0';  						-- In Simulation flag: 0 - real work (default), 1 - simulation
 		-- I2C parameters
-		I2C_SLAVE_ADDR	: std_logic_vector(6 downto 0) := "1010111"		-- Address of I2C slave, dafault 0x57
+		I2C_SLAVE_ADDR	: std_logic_vector(6 downto 0) := "1010111"	-- Address of I2C slave, dafault 0x57
 	);
 	port (
 		-- Clock and reset
@@ -33,7 +33,7 @@ entity sim_switcher_top is
 		cpu_jtag_rstn_o	: out	std_logic;
 
 		-- FPGA interrupt to CPU
-		fpga_int_o			: out	std_logic;							-- FPGA_INTn_V18, PIN_F12, active high
+		fpga_int_o			: out	std_logic; -- FPGA_INTn_V18, PIN_F12, active high
 	
 		-- I2C slave interface
 		i2c_scl_io			: inout	std_logic;
@@ -106,23 +106,23 @@ architecture rtl of sim_switcher_top is
 		);
 	end component;
 
-	constant FLASHES					: natural := 5;					-- Number of LED flashes on boot
+	constant FLASHES					: natural := 5;				-- Number of LED flashes on boot
-	constant CPU_RST_DURATION			: natural := 100_000_000;		-- 25_000_000 = 1sec
+	constant CPU_RST_DURATION			: natural := 100_000_000;	-- 25_000_000 = 1sec
-	constant PON_RST_DURATION			: natural := 10; 				-- 25_000_000 = 1sec
+	constant PON_RST_DURATION			: natural := 10; 			-- 25_000_000 = 1sec
-	constant PON_CPU_DELAY_DURATION		: natural := 75_000_000; 		-- 25_000_000 = 1sec
+	constant PON_CPU_DELAY_DURATION		: natural := 75_000_000; 	-- 25_000_000 = 1sec
-	constant SB_CONF_UPDATE_INTERVAL	: natural := 25_000_000; 		-- 25_000_000 = 1sec
+	constant SB_CONF_UPDATE_INTERVAL	: natural := 25_000_000; 	-- 25_000_000 = 1sec
 	
-	constant DEBOUNCING_WAIT_CYCLES	: natural := 3;						-- Number of debouncing wait cycles
+	constant DEBOUNCING_WAIT_CYCLES	: natural := 3;					-- Number of debouncing wait cycles
-	constant REPI2C_DEBOUNCING_WAIT_CYCLES	: natural := 3;				-- Number of debouncing wait cycles
+	constant REPI2C_DEBOUNCING_WAIT_CYCLES	: natural := 3;			-- Number of debouncing wait cycles
-	constant EXPIO_DEBOUNCING_WAIT_CYCLES	: natural := 25;			-- Number of debouncing wait cycles
+	constant EXPIO_DEBOUNCING_WAIT_CYCLES	: natural := 25;		-- Number of debouncing wait cycles
 
-	constant I2C_CLK             		: natural := 400_000;			-- speed the i2c bus (scl) will run at in Hz
+	constant I2C_CLK             		: natural := 400_000;		-- speed the i2c bus (scl) will run at in Hz
 
-	constant I2C_MAX_WAIT				: natural := 2_500_000;			-- 25_000_000 = 1sec
+	constant I2C_MAX_WAIT				: natural := 2_500_000;		-- 25_000_000 = 1sec
 
 	constant PSE_I2C_ADDR				: std_logic_vector(6 downto 0) := "0100000"; -- 0x20
 	constant PSE_REG_NUM				: natural := 8;
-	constant PSE_POLL_INTERVAL			: natural := 25_000_000;		-- 25_000_000 = 1sec
+	constant PSE_POLL_INTERVAL			: natural := 25_000_000;	-- 25_000_000 = 1sec
 
 	signal s_clk_i      : std_logic; -- clock buffer
 	signal s_rstn_i     : std_logic; -- reset signal
@@ -272,15 +272,6 @@ begin
 	-- Drive FAN control signals
 	fan_o			<= reg_fan_ctl;
 
-	-- POE PD init
-	reg_poepd_status(2)				<= poe_in_vpres;
-	reg_poepd_status(1 downto 0)	<= poe_in_t2p(1 downto 0);
-	poe_in_enn						<= reg_poepd_ctl;
-
-	----------------------
-	-- Working with PSE --
-	----------------------
-
 	-- PSE init
 	pse_rst						<= reg_pse_ctl(0);
 	pse_vpwr_enn				<= reg_pse_ctl(1);
@@ -320,8 +311,9 @@ begin
 								7 => x"14"	-- R/W
 							);
 
-
+	------------------------------
-	-- PSE read trigger process
+	-- PSE read trigger process --
+	------------------------------
 	pse_readtrig_proc: process(clk25_i, s_rstn_i, wait_i2c_start, i2c_core_busy, pse_i2c_write_reg) is
 		variable wait_cnt : natural := 0;
 	begin
@@ -450,13 +442,13 @@ begin
                     end if;
 
                 when i2c_rd_wait =>
-                    if (s_i2c_busy_flag = '0') then									-- Indicates data read in last command is ready
+                    if (s_i2c_busy_flag = '0') then												-- Indicates data read in last command is ready
-						pse_regs_value(reg_num_rd)	<= s_i2c_data_rd;				-- Store received byte
+						pse_regs_value(reg_num_rd)	<= s_i2c_data_rd;							-- Store received byte
 						reg_num_rd := reg_num_rd + 1;
-                        if (reg_num_rd = PSE_REG_NUM) then							-- All regs are 1 byte length
+                        if (reg_num_rd = PSE_REG_NUM) then										-- All regs are 1 byte length
-                            i2c_state   <= wait_ack;								-- Transaction complete, go to next state in design
+                            i2c_state   <= wait_ack;											-- Transaction complete, go to next state in design
                         else
-                            i2c_state	<= i2c_trn_start;							-- Transaction complete, go to next state in design
+                            i2c_state	<= i2c_trn_start;										-- Transaction complete, go to next state in design
                         end if;
                     end if;
 
@@ -473,9 +465,45 @@ begin
         end if;
     end process pse_i2c_proc;
 
-	------------------------------------
+	-- pse_scl_rptr: odio_repeater
-	-- Working woth expansion card IO --
+	-- generic map (
-	------------------------------------
+	-- 	WAIT_CYCLES => REPI2C_DEBOUNCING_WAIT_CYCLES
+	-- )
+	-- port map (
+	-- 	clk			=> clk25_i,
+	-- 	rstn		=> s_rstn_i,
+	-- 	signal_n1	=> i2c_scl_io,
+	-- 	signal_n2	=> pse_i2c_scl_io
+	-- );
+
+	-- pse_sda_rptr: odio_repeater
+	-- generic map (
+	-- 	WAIT_CYCLES => REPI2C_DEBOUNCING_WAIT_CYCLES
+	-- )
+	-- port map (
+	-- 	clk			=> clk25_i,
+	-- 	rstn		=> s_rstn_i,
+	-- 	signal_n1	=> i2c_sda_io,
+	-- 	signal_n2	=> pse_i2c_sda_io
+	-- );
+
+	-- pse_i2c_rptr: i2c_repeater
+	-- generic map (
+	-- 	WAIT_CYCLES => REPI2C_DEBOUNCING_WAIT_CYCLES
+	-- )
+	-- port map (
+	-- 	clk			=> clk25_i,
+	-- 	rstn		=> s_rstn_i,
+	-- 	pr_scl	=> i2c_scl_io,
+	-- 	pr_sda	=> i2c_sda_io,
+	-- 	sec_scl	=> pse_i2c_scl_io,
+	-- 	sec_sda	=> pse_i2c_sda_io
+	-- );
+
+	-- POE PD init
+	reg_poepd_status(2)				<= poe_in_vpres;
+	reg_poepd_status(1 downto 0)	<= poe_in_t2p(1 downto 0);
+	poe_in_enn						<= reg_poepd_ctl;
 
 	-- Expansion card IO control
 	gen_expio_dbnc: for i in 0 to 5 generate
@@ -508,6 +536,8 @@ begin
 		signal_out => sdb_pse_intn
 	);
 
+----------------------------------------------
+
 	--------------------------
 	-- Interrupt generation --
 	--------------------------