diff --git a/sim_switcher_top.vhd b/sim_switcher_top.vhd
index db92eab..4bb07c7 100644
--- a/sim_switcher_top.vhd
+++ b/sim_switcher_top.vhd
@@ -276,93 +276,5 @@ begin
 
 		end if;
 	end process;
-
-
----------------------------------
------ SIM card emulation test ---
----------------------------------
---
---	-- Bidir sinals routing
---	gen_datalines: for i in 0 to 7 generate
---		s_sim_data_i(i)	<= sim_data_io(i);
---		sim_data_io(i)	<= '0' when s_sim_data_o(i) = '0' else 'Z';
---
---		s_mod_data_i(i)	<= mod_data_io(i);
---		mod_data_io(i)	<= '0' when s_mod_data_o(i) = '0' else 'Z';
---
---		-- Debounce data lines
---		mod_dat_i_debounce : debounce
---		generic map (
---			WAIT_CYCLES => DEBOUNCING_WAIT_CYCLES
---		)
---		port map (
---			clk        => clk25_i,
---			signal_in  => s_mod_data_i(i),
---			signal_out => sdb_mod_data_i(i)
---		);
---
---		sim_dat_i_debounce : debounce
---		generic map (
---			WAIT_CYCLES => DEBOUNCING_WAIT_CYCLES
---		)
---		port map (
---			clk        => clk25_i,
---			signal_in  => s_sim_data_i(i),
---			signal_out => sdb_sim_data_i(i)
---		);
---	
---	end generate gen_datalines;
---	
---	-- Route one-way signals from mod to SIM
---	sim_pwron_o <= (others => '1');--mod_pwron_i;
---	sim_rst_o	<= mod_rst_i;
---	sim_clk_o	<= mod_clk_i;
---	mod_detect_o(3 downto 0)	<= sim_detect_i(3 downto 0);
---
---	------------------
---	-- SIM repeater --
---	------------------
---	sims: for num in 0 to 7 generate
---		sim_rptr_proc: process(clk25_i) is
---		begin
---			if s_rstn_i = '0' then
---				s_sim_data_o(num)	<= '1';
---				s_mod_data_o(num)	<= '1';
---				sdb_sim_data_prev(num)	<= sdb_sim_data_i(num);
---				sdb_mod_data_prev(num)	<= sdb_mod_data_i(num);
---				state(num)				<= idle;
---				
---			elsif (rising_edge(clk25_i)) then
---				sdb_sim_data_prev(num)	<= sdb_sim_data_i(num);
---				sdb_mod_data_prev(num)	<= sdb_mod_data_i(num);
---
---				case state(num) is
---					when idle =>
---						if (sdb_mod_data_prev(num) = '1' and sdb_mod_data_i(num) = '0') then
---							s_sim_data_o(num)	<= '0';
---							state(num)	<= mod_to_sim;
---						elsif	(sdb_sim_data_prev(num) = '1' and sdb_sim_data_i(num) = '0') then
---							s_mod_data_o(num)	<= '0';
---							state(num)	<= sim_to_mod;
---						end if;
---
---					when mod_to_sim =>
---						if	(sdb_mod_data_prev(num) = '0' and sdb_mod_data_i(num) = '1') then
---							s_sim_data_o(num)	<= '1';
---							state(num)	<= idle;
---						end if;
---
---					when sim_to_mod =>
---						if	(sdb_sim_data_prev(num) = '0' and sdb_sim_data_i(num) = '1') then
---							s_mod_data_o(num)	<= '1';
---							state(num)	<= idle;
---						end if;
---
---				end case;
---
---			end if;
---		end process;
---	end generate sims;
-
 	
 end architecture rtl;