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Finished DRC

This commit is contained in:
Alexey Bazlaev 2024-05-24 17:43:26 +07:00
parent 94eec2590b
commit 8815970193
1 changed files with 12 additions and 8 deletions
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20
Controller/Controller.PrjPcb
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@ -55,7 +55,7 @@ AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
AnnotateOrder=0
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
@ -72,7 +72,7 @@ AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
AnnotateOrder=1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
@ -106,7 +106,7 @@ AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
AnnotateOrder=2
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
@ -123,7 +123,7 @@ AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
AnnotateOrder=3
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
@ -167,6 +167,10 @@ DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=
[GeneratedDocument1]
DocumentPath=Project Outputs for Controller\Design Rule Check - Controller.html
DItemRevisionGUID=
[Configuration1]
Name=Sources
ParameterCount=0
@ -301,7 +305,7 @@ OutputDefault23=0
[OutputGroup2]
Name=Simulator Outputs
Description=
TargetPrinter=Brother MFC-L2720DW series Printer
TargetPrinter=Brother Laser Type2 Class Driver
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
OutputType1=AdvSimNetlist
OutputName1=Mixed Sim
@ -959,11 +963,11 @@ Type6=2
Type7=0
Type8=1
Type9=1
Type10=1
Type10=0
Type11=2
Type12=2
Type13=2
Type14=1
Type14=0
Type15=1
Type16=1
Type17=1
@ -1039,7 +1043,7 @@ Type86=2
Type87=2
Type88=2
Type89=1
Type90=1
Type90=0
Type91=3
Type92=3
Type93=2