202 lines
12 KiB
C
202 lines
12 KiB
C
/*
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* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* -----------------------------------------------------------------------
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*
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* $Date: 25. May 2018
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* $Revision: V6.2
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*
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* Project: Ethernet Physical Layer Transceiver (PHY)
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* Definitions for DP83848C
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* -------------------------------------------------------------------- */
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#ifndef __PHY_DP83848C_H
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#define __PHY_DP83848C_H
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#include "Driver_ETH_PHY.h"
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/* Basic Registers */
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#define REG_BMCR 0x00 /* Basic Mode Control Register */
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#define REG_BMSR 0x01 /* Basic Mode Status Register */
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#define REG_PHYIDR1 0x02 /* PHY Identifier 1 */
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#define REG_PHYIDR2 0x03 /* PHY Identifier 2 */
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#define REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
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#define REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
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#define REG_ANER 0x06 /* Auto-Neg. Expansion Register */
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#define REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
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/* Extended Registers */
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#define REG_PHYSTS 0x10 /* Status Register */
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#define REG_MICR 0x11 /* MII Interrupt Control Register */
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#define REG_MISR 0x12 /* MII Interrupt Status Register */
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#define REG_FCSCR 0x14 /* False Carrier Sense Counter */
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#define REG_RECR 0x15 /* Receive Error Counter */
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#define REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
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#define REG_RBR 0x17 /* RMII and Bypass Register */
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#define REG_LEDCR 0x18 /* LED Direct Control Register */
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#define REG_PHYCR 0x19 /* PHY Control Register */
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#define REG_BTSCR 0x1A /* 10Base-T Status/Control Register */
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#define REG_CDBR1 0x1B /* CD Test Control and BIST Extens. */
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#define REG_EDCR 0x1D /* Energy Detect Control Register */
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/* Basic Mode Control Register */
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#define BMCR_RESET 0x8000 /* Software Reset */
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#define BMCR_LOOPBACK 0x4000 /* Loopback mode */
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#define BMCR_SPEED_SEL 0x2000 /* Speed Select (1=100Mb/s) */
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#define BMCR_ANEG_EN 0x1000 /* Auto Negotiation Enable */
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#define BMCR_POWER_DOWN 0x0800 /* Power Down */
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#define BMCR_ISOLATE 0x0400 /* Isolate Media interface */
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#define BMCR_REST_ANEG 0x0200 /* Restart Auto Negotiation */
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#define BMCR_DUPLEX 0x0100 /* Duplex Mode (1=Full duplex) */
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#define BMCR_COL_TEST 0x0080 /* Collision Test */
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/* Basic Mode Status Register */
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#define BMSR_100B_T4 0x8000 /* 100BASE-T4 Capable */
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#define BMSR_100B_TX_FD 0x4000 /* 100BASE-TX Full Duplex Capable */
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#define BMSR_100B_TX_HD 0x2000 /* 100BASE-TX Half Duplex Capable */
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#define BMSR_10B_T_FD 0x1000 /* 10BASE-T Full Duplex Capable */
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#define BMSR_10B_T_HD 0x0800 /* 10BASE-T Half Duplex Capable */
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#define BMSR_MF_PRE_SUP 0x0040 /* Preamble suppression Capable */
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#define BMSR_ANEG_COMPL 0x0020 /* Auto Negotiation Complete */
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#define BMSR_REM_FAULT 0x0010 /* Remote Fault */
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#define BMSR_ANEG_ABIL 0x0008 /* Auto Negotiation Ability */
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#define BMSR_LINK_STAT 0x0004 /* Link Status (1=established) */
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#define BMSR_JABBER_DET 0x0002 /* Jaber Detect */
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#define BMSR_EXT_CAPAB 0x0001 /* Extended Capability */
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/* PHY Identifier Registers */
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#define PHY_ID1 0x2000 /* DP83848C Device Identifier MSB */
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#define PHY_ID2 0x5C90 /* DP83848C Device Identifier LSB */
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/* PHY Status Register */
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#define PHYSTS_MDI_X 0x4000 /* MDI-X mode enabled by Auto-Negot. */
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#define PHYSTS_REC_ERR 0x2000 /* Receive Error Latch */
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#define PHYSTS_POL_STAT 0x1000 /* Polarity Status */
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#define PHYSTS_FC_SENSE 0x0800 /* False Carrier Sense Latch */
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#define PHYSTS_SIG_DET 0x0400 /* 100Base-TX Signal Detect */
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#define PHYSTS_DES_LOCK 0x0200 /* 100Base-TX Descrambler Lock */
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#define PHYSTS_PAGE_REC 0x0100 /* Link Code Word Page Received */
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#define PHYSTS_MII_INT 0x0080 /* MII Interrupt Pending */
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#define PHYSTS_REM_FAULT 0x0040 /* Remote Fault */
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#define PHYSTS_JABBER_DET 0x0020 /* Jabber Detect */
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#define PHYSTS_ANEG_COMPL 0x0010 /* Auto Negotiation Complete */
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#define PHYSTS_LOOPBACK 0x0008 /* Loopback Status */
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#define PHYSTS_DUPLEX 0x0004 /* Duplex Status (1=Full duplex) */
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#define PHYSTS_SPEED 0x0002 /* Speed10 Status (1=10MBit/s) */
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#define PHYSTS_LINK_STAT 0x0001 /* Link Status (1=established) */
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/* MII Interrupt Control Register */
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#define MICR_TINT 0x0004 /* Test Interrupt */
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#define MICR_INTEN 0x0002 /* Interrupt Enable */
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#define MICR_INT_OE 0x0001 /* Interrupt Output Enable */
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/* MII Interrupt Status Register */
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#define MISR_ED_INT 0x4000 /* Energy Detect Interrupt */
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#define MISR_LINK_INT 0x2000 /* Link Status Change Interrupt */
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#define MISR_SPD_INT 0x1000 /* Speed Status Change Interrupt */
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#define MISR_DUP_INT 0x0800 /* Duplex Status Change Interrupt */
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#define MISR_ANC_INT 0x0400 /* Auto Negotiation Complete Interr. */
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#define MISR_FHF_INT 0x0200 /* False Carrier Counter HF Interrupt*/
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#define MISR_RHF_INT 0x0100 /* Receive Error Counter HF Interrupt*/
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#define MISR_ED_INT_EN 0x0040 /* Endrgy Detect Int.Enable */
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#define MISR_LINK_INT_EN 0x0020 /* Link Status Change Int.Enable */
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#define MISR_SPD_INT_EN 0x0010 /* Speed Status Change Int.Enable */
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#define MISR_DUP_INT_EN 0x0008 /* Duplex Status Change Int.Enable */
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#define MISR_ANC_INT_EN 0x0004 /* Auto Negotiation Complete Int.Ena.*/
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#define MISR_FHF_INT_EN 0x0002 /* False Carrier Count.HF Int.Enable */
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#define MISR_RHF_INT_EN 0x0001 /* Receive Error Count.HF Int.Enable */
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/* 100Mb/s PCS Configuration and Status Register */
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#define PCSR_TQ_EN 0x0400 /* 100Mbs True Quiet Mode Enable */
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#define PCSR_SD_FORCE_PMA 0x0200 /* Signal Detect Force PMA */
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#define PCSR_SD_OPTION 0x0100 /* Signal Detect Option */
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#define PCSR_DESC_TIME 0x0080 /* Descrambler Timeout */
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#define PCSR_FORCE_100_OK 0x0020 /* Force 100Mb/s Good Link */
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#define PCSR_NRZI_BYPASS 0x0004 /* NRZI Bypass Enable */
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/* RMII and Bypass Register */
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#define RBR_RMII_MODE 0x0020 /* Reduced MII Mode */
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#define RBR_RMII_REV1_0 0x0010 /* Reduced MII Revision 1.0 */
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#define RBR_RX_OVF_STS 0x0008 /* RX FIFO Overflow Status */
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#define RBR_RX_UNF_STS 0x0004 /* RX FIFO Underflow Status */
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#define RBR_ELAST_BUF 0x0003 /* Receive Elasticity Buffer */
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/* LED Direct Control Register */
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#define LEDCR_DRV_SPDLED 0x0020 /* Drive SPDLED bit to LED_SPD output*/
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#define LEDCR_DRV_LNKLED 0x0010 /* Drive LNKLED bit to LED_LNK output*/
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#define LEDCR_DRV_ACTLED 0x0008 /* Drive ACTLED bit to LED_ACT output*/
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#define LEDCR_SPDLED 0x0004 /* Value to force on LED_SPD output */
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#define LEDCR_LNKLED 0x0002 /* Value to force on LED_LNK output */
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#define LEDCR_ACTLED 0x0001 /* Value to force on LED_ACT output */
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/* PHY Control Register */
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#define PHYCR_MDIX_EN 0x8000 /* Auto MDIX Enable */
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#define PHYCR_FORCE_MDIX 0x4000 /* Force MDIX */
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#define PHYCR_PAUSE_RX 0x2000 /* Pause Receive Negotiated */
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#define PHYCR_PAUSE_TX 0x1000 /* Pause Transmit Negotiated */
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#define PHYCR_BIST_FE 0x0800 /* BIST Force Error */
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#define PHYCR_PSR_15 0x0400 /* BIST Sequence select */
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#define PHYCR_BIST_STATUS 0x0200 /* BIST Test Status */
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#define PHYCR_BIST_START 0x0100 /* BIST Start */
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#define PHYCR_BP_STRETCH 0x0080 /* Bypass LED Stretching */
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#define PHYCR_LED_CNFG 0x0060 /* LEDs Configuration */
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#define PHYCR_PHYADDR 0x001F /* PHY Address for port */
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/* 10Base-T Status/Control Register */
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#define BTSCR_10BT_SER 0x8000 /* 10Base-T Serial Mode */
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#define BTSCR_SQUELCH 0x0E00 /* Squelch Configuration */
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#define BTSCR_LOOPB10_DIS 0x0100 /* Loopback 10Base-T Disable */
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#define BTSCR_LP_DIS 0x0080 /* Normal Link Pulse Disable */
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#define BTSCR_FORCE_LNK10 0x0040 /* Force 10Mbs Good Link */
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#define BTSCR_POLARITY 0x0010 /* 10Mbs Polarity Status */
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#define BTSCR_HEARTB_DIS 0x0002 /* Heartbeat Disable */
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#define BTSCR_JABBER_DIS 0x0001 /* Jabber Disable */
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/* CD Test and BIST Extensions Register */
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#define CDBR1_BIST_ERR_CNTR 0xFF00 /* BIST ERROR Counter */
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#define CDBR1_BIST_CONT_MD 0x0020 /* Packet BIST Continuous Mode */
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#define CDBR1_CDPATEN10 0x0010 /* CD Pattern Enable for 10Mbs */
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#define CDBR1_10MEG_PAT_GAP 0x0004 /* Defines gap between data or NLP */
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#define CDBR1_CDPATTSEL 0x0003 /* CD Pattern Select */
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/* Energy Detect Control */
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#define EDCR_ED_EN 0x8000 /* Energy Detect Enable */
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#define EDCR_ED_AUTO_UP 0x4000 /* Energy Detect Automatic Power Up */
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#define EDCR_ED_AUTO_DOWN 0x2000 /* Energy Detect Automatic Power Down*/
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#define EDCR_ED_MAN 0x1000 /* Energy Detect Manual Power Up/Down*/
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#define EDCR_ED_BURST_DIS 0x0800 /* Energy Detect Burst Disable */
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#define EDCR_ED_PWR_STATE 0x0400 /* Energy Detect Power State */
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#define EDCR_ED_ERR_MET 0x0200 /* Energy Detect Error Threshold Met */
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#define EDCR_ED_DATA_MET 0x0100 /* Energy Detect Data Threshold Met */
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#define EDCR_ED_ERR_CNT 0x00F0 /* Energy Detect Error Threshold */
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#define EDCR_ED_DATA_CNT 0x000F /* Energy Detect Data Threshold */
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/* PHY Driver State Flags */
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#define PHY_INIT 0x01U /* Driver initialized */
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#define PHY_POWER 0x02U /* Driver power is on */
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/* PHY Driver Control Structure */
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typedef struct phy_ctrl {
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ARM_ETH_PHY_Read_t reg_rd; /* PHY register read function */
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ARM_ETH_PHY_Write_t reg_wr; /* PHY register write function */
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uint16_t bmcr; /* BMCR register value */
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uint8_t flags; /* Control flags */
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uint8_t rsvd; /* Reserved */
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} PHY_CTRL;
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#endif /* __PHY_DP83848C_H */
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