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Added STM32 ETH_HAL

This commit is contained in:
Alexey Bazlaev 2023-01-30 14:16:19 +07:00
parent 8648d1a687
commit 6a03d6e017
8 changed files with 2503 additions and 88 deletions
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2
FreeRTOS/source/include/FreeRTOSIPConfig.h
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@ -39,7 +39,7 @@
/* It is not sensible for this macro to have a default value as it is hardware
* dependent. */
#define ipconfigBYTE_ORDER pdFREERTOS_LITTLE_ENDIAN
#define ipconfigUSE_NETWORK_EVENT_HOOK 1
#endif

280
FreeRTOS/source/include/NetworkInterface.h
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@ -28,12 +28,292 @@
#ifndef NETWORK_INTERFACE_H
#define NETWORK_INTERFACE_H
#include "stdio.h"
#include "stdint.h"
/* *INDENT-OFF* */
#ifdef __cplusplus
extern "C" {
#endif
/* *INDENT-ON* */
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */
HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */
HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */
HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */
HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
} HAL_ETH_StateTypeDef;
/**
* @brief ETH Init Structure definition
*/
typedef struct
{
uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
* The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
* and the mode (half/full-duplex).
* This parameter can be a value of @ref ETH_AutoNegotiation */
uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
* This parameter can be a value of @ref ETH_Speed */
uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
* This parameter can be a value of @ref ETH_Duplex_Mode */
uint16_t PhyAddress; /*!< Ethernet PHY address.
* This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
uint8_t * MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
* This parameter can be a value of @ref ETH_Rx_Mode */
uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
* This parameter can be a value of @ref ETH_Checksum_Mode */
uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface.
* This parameter can be a value of @ref ETH_Media_Interface */
} ETH_InitTypeDef;
/**
* @brief ETH MAC Configuration Structure definition
*/
typedef struct
{
uint32_t Watchdog; /*!< Selects or not the Watchdog timer
* When enabled, the MAC allows no more then 2048 bytes to be received.
* When disabled, the MAC can receive up to 16384 bytes.
* This parameter can be a value of @ref ETH_Watchdog */
uint32_t Jabber; /*!< Selects or not Jabber timer
* When enabled, the MAC allows no more then 2048 bytes to be sent.
* When disabled, the MAC can send up to 16384 bytes.
* This parameter can be a value of @ref ETH_Jabber */
uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
* This parameter can be a value of @ref ETH_Inter_Frame_Gap */
uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
* This parameter can be a value of @ref ETH_Carrier_Sense */
uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
* ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
* in Half-Duplex mode.
* This parameter can be a value of @ref ETH_Receive_Own */
uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
* This parameter can be a value of @ref ETH_Loop_Back_Mode */
uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
* This parameter can be a value of @ref ETH_Checksum_Offload */
uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
* when a collision occurs (Half-Duplex mode).
* This parameter can be a value of @ref ETH_Retry_Transmission */
uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
* This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
* This parameter can be a value of @ref ETH_Back_Off_Limit */
uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
* This parameter can be a value of @ref ETH_Deferral_Check */
uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
* This parameter can be a value of @ref ETH_Receive_All */
uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
* This parameter can be a value of @ref ETH_Source_Addr_Filter */
uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
* This parameter can be a value of @ref ETH_Pass_Control_Frames */
uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
* This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
* This parameter can be a value of @ref ETH_Destination_Addr_Filter */
uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
* This parameter can be a value of @ref ETH_Promiscuous_Mode */
uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
* This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
* This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
* This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
* This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
* This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
* This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
* automatic retransmission of PAUSE Frame.
* This parameter can be a value of @ref ETH_Pause_Low_Threshold */
uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
* unicast address and unique multicast address).
* This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
* disable its transmitter for a specified time (Pause Time)
* This parameter can be a value of @ref ETH_Receive_Flow_Control */
uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
* or the MAC back-pressure operation (Half-Duplex mode)
* This parameter can be a value of @ref ETH_Transmit_Flow_Control */
uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
* comparison and filtering.
* This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
} ETH_MACInitTypeDef;
/**
* @brief ETH DMA Configuration Structure definition
*/
typedef struct
{
uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
* This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
* This parameter can be a value of @ref ETH_Receive_Store_Forward */
uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
* This parameter can be a value of @ref ETH_Flush_Received_Frame */
uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
* This parameter can be a value of @ref ETH_Transmit_Store_Forward */
uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
* This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
* This parameter can be a value of @ref ETH_Forward_Error_Frames */
uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
* and length less than 64 bytes) including pad-bytes and CRC)
* This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
* This parameter can be a value of @ref ETH_Receive_Threshold_Control */
uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
* frame of Transmit data even before obtaining the status for the first frame.
* This parameter can be a value of @ref ETH_Second_Frame_Operate */
uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
* This parameter can be a value of @ref ETH_Address_Aligned_Beats */
uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
* This parameter can be a value of @ref ETH_Fixed_Burst */
uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
* This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
* This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
* This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
* This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
* This parameter can be a value of @ref ETH_DMA_Arbitration */
} ETH_DMAInitTypeDef;
/**
* @brief ETH DMA Descriptors data structure definition
*/
typedef struct
{
volatile uint32_t Status; /*!< Status */
uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
/*!< Enhanced Ethernet DMA PTP Descriptors */
uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */
uint32_t Reserved1; /*!< Reserved */
uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */
uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */
} ETH_DMADescTypeDef;
/**
* @brief Received Frame Informations structure definition
*/
typedef struct
{
ETH_DMADescTypeDef * FSRxDesc; /*!< First Segment Rx Desc */
ETH_DMADescTypeDef * LSRxDesc; /*!< Last Segment Rx Desc */
uint32_t SegCount; /*!< Segment count */
uint32_t length; /*!< Frame length */
uint32_t buffer; /*!< Frame buffer */
} ETH_DMARxFrameInfos;
#define ETH_TypeDef void
/**
* @brief ETH Handle Structure definition
*/
typedef struct
{
ETH_TypeDef * Instance; /*!< Register base address */
ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
uint32_t LinkStatus; /*!< Ethernet link status */
ETH_DMADescTypeDef * RxDesc; /*!< Rx descriptor to Get */
ETH_DMADescTypeDef * TxDesc; /*!< Tx descriptor to Set */
ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
volatile HAL_ETH_StateTypeDef State; /*!< ETH communication state */
HAL_LockTypeDef Lock; /*!< ETH Lock */
} ETH_HandleTypeDef;
/* INTERNAL API FUNCTIONS. */
BaseType_t xNetworkInterfaceInitialise( void );
BaseType_t xNetworkInterfaceOutput( NetworkBufferDescriptor_t * const pxNetworkBuffer,

1296
FreeRTOS/source/portable/NetworkInterface/board_family/NetworkInterface.c
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737
RTE/Device/GD32F107VC/gd32f10x_dma.c Normal file
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@ -0,0 +1,737 @@
/*!
\file gd32f10x_dma.c
\brief DMA driver
\version 2014-12-26, V1.0.0, firmware for GD32F10x
\version 2017-06-20, V2.0.0, firmware for GD32F10x
\version 2018-07-31, V2.1.0, firmware for GD32F10x
\version 2019-10-30, V2.1.1, firmware for GD32F10x
\version 2020-09-30, V2.2.0, firmware for GD32F10x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32f10x_dma.h"
#define DMA_WRONG_HANDLE while(1){}
/* check whether peripheral matches channels or not */
static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx);
/*!
\brief deinitialize DMA a channel registers
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel is deinitialized
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
/* disable DMA a channel */
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
/* reset DMA channel registers */
DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE;
DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE;
DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE;
DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE;
DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx);
}
/*!
\brief initialize the parameters of DMA struct with the default values
\param[in] init_struct: the initialization data needed to initialize DMA channel
\param[out] none
\retval none
*/
void dma_struct_para_init(dma_parameter_struct* init_struct)
{
/* set the DMA struct with the default values */
init_struct->periph_addr = 0U;
init_struct->periph_width = 0U;
init_struct->periph_inc = DMA_PERIPH_INCREASE_DISABLE;
init_struct->memory_addr = 0U;
init_struct->memory_width = 0U;
init_struct->memory_inc = DMA_MEMORY_INCREASE_DISABLE;
init_struct->number = 0U;
init_struct->direction = DMA_PERIPHERAL_TO_MEMORY;
init_struct->priority = DMA_PRIORITY_LOW;
}
/*!
\brief initialize DMA channel
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel is initialized
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] init_struct: the data needed to initialize DMA channel
periph_addr: peripheral base address
periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT
periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE
memory_addr: memory base address
memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT
memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE
direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL
number: the number of remaining data to be transferred by the DMA
priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH
\param[out] none
\retval none
*/
void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct)
{
uint32_t ctl;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
/* configure peripheral base address */
DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr;
/* configure memory base address */
DMA_CHMADDR(dma_periph, channelx) = init_struct->memory_addr;
/* configure the number of remaining data to be transferred */
DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK);
/* configure peripheral transfer width,memory transfer width, */
ctl = DMA_CHCTL(dma_periph, channelx);
ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO);
ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority);
DMA_CHCTL(dma_periph, channelx) = ctl;
/* configure peripheral increasing mode */
if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
}else{
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
}
/* configure memory increasing mode */
if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
}else{
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
}
/* configure the direction of data transfer */
if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction){
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
}else{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
}
}
/*!
\brief enable DMA circulation mode
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN;
}
/*!
\brief disable DMA circulation mode
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN;
}
/*!
\brief enable memory to memory mode
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M;
}
/*!
\brief disable memory to memory mode
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M;
}
/*!
\brief enable DMA channel
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN;
}
/*!
\brief disable DMA channel
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
}
/*!
\brief set DMA peripheral base address
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to set peripheral base address
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] address: peripheral base address
\param[out] none
\retval none
*/
void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHPADDR(dma_periph, channelx) = address;
}
/*!
\brief set DMA memory base address
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to set memory base address
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] address: memory base address
\param[out] none
\retval none
*/
void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHMADDR(dma_periph, channelx) = address;
}
/*!
\brief set the number of remaining data to be transferred by the DMA
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to set number
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] number: the number of remaining data to be transferred by the DMA
\arg 0x0000-0xFFFF
\param[out] none
\retval none
*/
void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK);
}
/*!
\brief get the number of remaining data to be transferred by the DMA
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to set number
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval uint32_t: the number of remaining data to be transferred by the DMA
*/
uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
return (uint32_t)DMA_CHCNT(dma_periph, channelx);
}
/*!
\brief configure priority level of DMA channel
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] priority: priority Level of this channel
only one parameter can be selected which is shown as below:
\arg DMA_PRIORITY_LOW: low priority
\arg DMA_PRIORITY_MEDIUM: medium priority
\arg DMA_PRIORITY_HIGH: high priority
\arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority
\param[out] none
\retval none
*/
void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority)
{
uint32_t ctl;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
/* acquire DMA_CHxCTL register */
ctl = DMA_CHCTL(dma_periph, channelx);
/* assign regiser */
ctl &= ~DMA_CHXCTL_PRIO;
ctl |= priority;
DMA_CHCTL(dma_periph, channelx) = ctl;
}
/*!
\brief configure transfer data size of memory
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] mwidth: transfer data width of memory
only one parameter can be selected which is shown as below:
\arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit
\arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit
\arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit
\param[out] none
\retval none
*/
void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth)
{
uint32_t ctl;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
/* acquire DMA_CHxCTL register */
ctl = DMA_CHCTL(dma_periph, channelx);
/* assign regiser */
ctl &= ~DMA_CHXCTL_MWIDTH;
ctl |= mwidth;
DMA_CHCTL(dma_periph, channelx) = ctl;
}
/*!
\brief configure transfer data size of peripheral
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] pwidth: transfer data width of peripheral
only one parameter can be selected which is shown as below:
\arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit
\arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit
\arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit
\param[out] none
\retval none
*/
void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth)
{
uint32_t ctl;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
/* acquire DMA_CHxCTL register */
ctl = DMA_CHCTL(dma_periph, channelx);
/* assign regiser */
ctl &= ~DMA_CHXCTL_PWIDTH;
ctl |= pwidth;
DMA_CHCTL(dma_periph, channelx) = ctl;
}
/*!
\brief enable next address increasement algorithm of memory
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
}
/*!
\brief disable next address increasement algorithm of memory
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
}
/*!
\brief enable next address increasement algorithm of peripheral
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
}
/*!
\brief disable next address increasement algorithm of peripheral
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
}
/*!
\brief configure the direction of data transfer on the channel
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] direction: specify the direction of data transfer
only one parameter can be selected which is shown as below:
\arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory
\arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral
\param[out] none
\retval none
*/
void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
if(DMA_PERIPHERAL_TO_MEMORY == direction){
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
} else {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
}
}
/*!
\brief check DMA flag is set or not
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to get flag
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] flag: specify get which flag
only one parameter can be selected which is shown as below:
\arg DMA_FLAG_G: global interrupt flag of channel
\arg DMA_FLAG_FTF: full transfer finish flag of channel
\arg DMA_FLAG_HTF: half transfer finish flag of channel
\arg DMA_FLAG_ERR: error flag of channel
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{
FlagStatus reval;
/* check whether the flag is set or not */
if(RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))){
reval = SET;
}else{
reval = RESET;
}
return reval;
}
/*!
\brief clear the flag of a DMA channel
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to clear flag
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] flag: specify get which flag
only one parameter can be selected which is shown as below:
\arg DMA_FLAG_G: global interrupt flag of channel
\arg DMA_FLAG_FTF: full transfer finish flag of channel
\arg DMA_FLAG_HTF: half transfer finish flag of channel
\arg DMA_FLAG_ERR: error flag of channel
\param[out] none
\retval none
*/
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{
DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
}
/*!
\brief check DMA flag and interrupt enable bit is set or not
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to get flag
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] flag: specify get which flag
only one parameter can be selected which is shown as below:
\arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
\arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
\arg DMA_INT_FLAG_ERR: error interrupt flag of channel
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{
uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
switch(flag){
case DMA_INT_FLAG_FTF:
/* check whether the full transfer finish interrupt flag is set and enabled */
interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE;
break;
case DMA_INT_FLAG_HTF:
/* check whether the half transfer finish interrupt flag is set and enabled */
interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE;
break;
case DMA_INT_FLAG_ERR:
/* check whether the error interrupt flag is set and enabled */
interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE;
break;
default:
DMA_WRONG_HANDLE
}
/* when the interrupt flag is set and enabled, return SET */
if(interrupt_flag && interrupt_enable){
return SET;
}else{
return RESET;
}
}
/*!
\brief clear DMA a channel flag
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to clear flag
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] flag: specify get which flag
only one parameter can be selected which is shown as below:
\arg DMA_INT_FLAG_G: global interrupt flag of channel
\arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
\arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
\arg DMA_INT_FLAG_ERR: error interrupt flag of channel
\param[out] none
\retval none
*/
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{
DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
}
/*!
\brief enable DMA interrupt
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] source: specify which interrupt to enbale
one or more parameters can be selected which are shown as below
\arg DMA_INT_FTF: channel full transfer finish interrupt
\arg DMA_INT_HTF: channel half transfer finish interrupt
\arg DMA_INT_ERR: channel error interrupt
\param[out] none
\retval none
*/
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) |= source;
}
/*!
\brief disable DMA interrupt
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] source: specify which interrupt to disbale
one or more parameters can be selected which are shown as below
\arg DMA_INT_FTF: channel full transfer finish interrupt
\arg DMA_INT_HTF: channel half transfer finish interrupt
\arg DMA_INT_ERR: channel error interrupt
\param[out] none
\retval none
*/
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) &= ~source;
}
/*!
\brief check whether peripheral and channels match
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA_CHx(x=0..6)
\param[out] none
\retval ErrStatus: SUCCESS or ERROR
*/
static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx)
{
ErrStatus val = SUCCESS;
if(DMA1 == dma_periph){
/* for DMA1, the channel is from DMA_CH0 to DMA_CH4 */
if(channelx > DMA_CH4){
val = ERROR;
}
}
return val;
}

2
RTE/_Target_1/RTE_Components.h
View File

@ -24,6 +24,8 @@
#define RTE_RTOS_FreeRTOS_EVENTGROUPS /* RTOS FreeRTOS Event Groups */
/* ARM.FreeRTOS::RTOS:Heap:Heap_2:10.5.1 */
#define RTE_RTOS_FreeRTOS_HEAP_2 /* RTOS FreeRTOS Heap 2 */
/* GigaDevice::Device:GD32F10x_StdPeripherals:DMA:2.0.2 */
#define RTE_DEVICE_STDPERIPHERALS_DMA
/* GigaDevice::Device:GD32F10x_StdPeripherals:ENET:2.0.2 */
#define RTE_DEVICE_STDPERIPHERALS_ENET
/* GigaDevice::Device:GD32F10x_StdPeripherals:EXTI:2.0.2 */

159
Test_project_for_GD32107C-EVAL.uvguix.right
View File

File diff suppressed because one or more lines are too long

114
Test_project_for_GD32107C-EVAL.uvoptx
View File

@ -153,13 +153,115 @@
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL040000 -FP0($$Device:GD32F107VC$Flash\GD32F10x_CL.FLM))</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Breakpoint>
<Bp>
<Number>0</Number>
<Type>0</Type>
<LineNumber>476</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>0</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>0</BreakIfRCount>
<Filename>C:/Users/User/AppData/Local/Arm/Packs/ARM/CMSIS-FreeRTOS/10.5.1/Source/event_groups.c</Filename>
<ExecCommand></ExecCommand>
<Expression></Expression>
</Bp>
<Bp>
<Number>1</Number>
<Type>0</Type>
<LineNumber>75</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>0</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>0</BreakIfRCount>
<Filename>.\FreeRTOS\source\portable\NetworkInterface\board_family\NetworkInterface.c</Filename>
<ExecCommand></ExecCommand>
<Expression></Expression>
</Bp>
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<Number>2</Number>
<Type>0</Type>
<LineNumber>64</LineNumber>
<EnabledFlag>1</EnabledFlag>
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<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
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<BreakIfRCount>0</BreakIfRCount>
<Filename>.\FreeRTOS\source\portable\NetworkInterface\board_family\NetworkInterface.c</Filename>
<ExecCommand></ExecCommand>
<Expression></Expression>
</Bp>
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<Number>3</Number>
<Type>0</Type>
<LineNumber>57</LineNumber>
<EnabledFlag>1</EnabledFlag>
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<ByteObject>0</ByteObject>
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<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
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<Filename>.\FreeRTOS\source\portable\NetworkInterface\board_family\NetworkInterface.c</Filename>
<ExecCommand></ExecCommand>
<Expression></Expression>
</Bp>
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<Number>4</Number>
<Type>0</Type>
<LineNumber>243</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>0</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>0</BreakIfRCount>
<Filename>.\main.c</Filename>
<ExecCommand></ExecCommand>
<Expression></Expression>
</Bp>
<Bp>
<Number>5</Number>
<Type>0</Type>
<LineNumber>221</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>0</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>0</BreakIfRCount>
<Filename>.\main.c</Filename>
<ExecCommand></ExecCommand>
<Expression></Expression>
</Bp>
</Breakpoint>
<WatchWindow1>
<Ww>
<count>0</count>
<WinNumber>1</WinNumber>
<ItemText>tickCounter</ItemText>
</Ww>
<Ww>
<count>1</count>
<WinNumber>1</WinNumber>
<ItemText>xBoundTCPSocketsList</ItemText>
</Ww>
</WatchWindow1>
<MemoryWindow1>
<Mm>
@ -229,7 +331,7 @@
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\main.c</PathWithFileName>
@ -241,7 +343,7 @@
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\DemoTasks\SimpleTCPEchoServer.c</PathWithFileName>
@ -297,7 +399,7 @@
<GroupNumber>2</GroupNumber>
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\FreeRTOS\source\FreeRTOS_IP.c</PathWithFileName>
@ -501,7 +603,7 @@
<GroupNumber>2</GroupNumber>
<FileNumber>23</FileNumber>
<FileType>1</FileType>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\FreeRTOS\source\FreeRTOS_TCP_Utils.c</PathWithFileName>
@ -613,7 +715,7 @@
<Group>
<GroupName>::RTOS</GroupName>
<tvExp>0</tvExp>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>

1
main.c
View File

@ -219,6 +219,7 @@ int main(void)
xTaskCreate( vTaskToggleLed, "ToggleLed", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY+1, NULL);
xTaskCreate( vTaskHelloWorld, "HelloWorld", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY+1, NULL);
FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress );
vStartSimpleTCPServerTasks( configMINIMAL_STACK_SIZE*2, tskIDLE_PRIORITY+1 );
vTaskStartScheduler();
while(1);
}