Added RTC module
This commit is contained in:
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24bac1d060
commit
29b097016f
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/*!
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\file gd32f10x_rtc.c
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\brief RTC driver
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\version 2014-12-26, V1.0.0, firmware for GD32F10x
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\version 2017-06-20, V2.0.0, firmware for GD32F10x
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\version 2018-07-31, V2.1.0, firmware for GD32F10x
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\version 2020-09-30, V2.2.0, firmware for GD32F10x
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*/
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/*
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Copyright (c) 2020, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "gd32f10x_rtc.h"
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/* RTC register high / low bits mask */
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#define RTC_HIGH_BITS_MASK ((uint32_t)0x000F0000U) /* RTC high bits mask */
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#define RTC_LOW_BITS_MASK ((uint32_t)0x0000FFFFU) /* RTC low bits mask */
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/* RTC register high bits offset */
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#define RTC_HIGH_BITS_OFFSET ((uint32_t)16U)
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/*!
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\brief enter RTC configuration mode
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\param[in] none
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\param[out] none
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\retval none
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*/
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void rtc_configuration_mode_enter(void)
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{
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RTC_CTL |= RTC_CTL_CMF;
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}
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/*!
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\brief exit RTC configuration mode
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\param[in] none
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\param[out] none
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\retval none
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*/
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void rtc_configuration_mode_exit(void)
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{
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RTC_CTL &= ~RTC_CTL_CMF;
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}
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/*!
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\brief set RTC counter value
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\param[in] cnt: RTC counter value
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\param[out] none
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\retval none
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*/
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void rtc_counter_set(uint32_t cnt)
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{
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rtc_configuration_mode_enter();
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/* set the RTC counter high bits */
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RTC_CNTH = (cnt >> RTC_HIGH_BITS_OFFSET);
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/* set the RTC counter low bits */
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RTC_CNTL = (cnt & RTC_LOW_BITS_MASK);
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rtc_configuration_mode_exit();
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}
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/*!
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\brief set RTC prescaler value
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\param[in] psc: RTC prescaler value
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\param[out] none
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\retval none
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*/
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void rtc_prescaler_set(uint32_t psc)
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{
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rtc_configuration_mode_enter();
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/* set the RTC prescaler high bits */
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RTC_PSCH = ((psc & RTC_HIGH_BITS_MASK) >> RTC_HIGH_BITS_OFFSET);
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/* set the RTC prescaler low bits */
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RTC_PSCL = (psc & RTC_LOW_BITS_MASK);
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rtc_configuration_mode_exit();
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}
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/*!
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\brief wait RTC last write operation finished flag set
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\param[in] none
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\param[out] none
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\retval none
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*/
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void rtc_lwoff_wait(void)
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{
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/* loop until LWOFF flag is set */
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while(RESET == (RTC_CTL & RTC_CTL_LWOFF)){
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}
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}
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/*!
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\brief wait RTC registers synchronized flag set
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\param[in] none
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\param[out] none
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\retval none
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*/
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void rtc_register_sync_wait(void)
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{
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/* clear RSYNF flag */
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RTC_CTL &= ~RTC_CTL_RSYNF;
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/* loop until RSYNF flag is set */
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while(RESET == (RTC_CTL & RTC_CTL_RSYNF)){
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}
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}
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/*!
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\brief set RTC alarm value
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\param[in] alarm: RTC alarm value
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\param[out] none
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\retval none
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*/
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void rtc_alarm_config(uint32_t alarm)
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{
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rtc_configuration_mode_enter();
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/* set the alarm high bits */
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RTC_ALRMH = (alarm >> RTC_HIGH_BITS_OFFSET);
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/* set the alarm low bits */
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RTC_ALRML = (alarm & RTC_LOW_BITS_MASK);
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rtc_configuration_mode_exit();
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}
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/*!
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\brief get RTC counter value
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\param[in] none
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\param[out] none
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\retval RTC counter value
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*/
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uint32_t rtc_counter_get(void)
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{
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uint32_t temp = 0x0U;
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temp = RTC_CNTL;
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temp |= (RTC_CNTH << RTC_HIGH_BITS_OFFSET);
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return temp;
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}
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/*!
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\brief get RTC divider value
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\param[in] none
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\param[out] none
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\retval RTC divider value
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*/
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uint32_t rtc_divider_get(void)
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{
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uint32_t temp = 0x00U;
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temp = ((RTC_DIVH & RTC_DIVH_DIV) << RTC_HIGH_BITS_OFFSET);
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temp |= RTC_DIVL;
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return temp;
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}
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/*!
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\brief get RTC flag status
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\param[in] flag: specify which flag status to get
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only one parameter can be selected which is shown as below:
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\arg RTC_FLAG_SECOND: second interrupt flag
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\arg RTC_FLAG_ALARM: alarm interrupt flag
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\arg RTC_FLAG_OVERFLOW: overflow interrupt flag
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\arg RTC_FLAG_RSYN: registers synchronized flag
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\arg RTC_FLAG_LWOF: last write operation finished flag
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\param[out] none
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\retval SET or RESET
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*/
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FlagStatus rtc_flag_get(uint32_t flag)
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{
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if(RESET != (RTC_CTL & flag)){
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return SET;
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}else{
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return RESET;
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}
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}
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/*!
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\brief clear RTC flag status
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\param[in] flag: specify which flag status to clear
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one or more parameters can be selected which are shown as below:
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\arg RTC_FLAG_SECOND: second interrupt flag
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\arg RTC_FLAG_ALARM: alarm interrupt flag
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\arg RTC_FLAG_OVERFLOW: overflow interrupt flag
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\arg RTC_FLAG_RSYN: registers synchronized flag
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\param[out] none
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\retval none
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*/
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void rtc_flag_clear(uint32_t flag)
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{
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/* clear RTC flag */
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RTC_CTL &= ~flag;
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}
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/*!
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\brief get RTC interrupt flag status
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\param[in] flag: specify which flag status to get
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only one parameter can be selected which is shown as below:
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\arg RTC_INT_FLAG_SECOND: second interrupt flag
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\arg RTC_INT_FLAG_ALARM: alarm interrupt flag
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\arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag
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\param[out] none
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\retval SET or RESET
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*/
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FlagStatus rtc_interrupt_flag_get(uint32_t flag)
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{
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if(RESET != (RTC_CTL & flag)){
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return SET;
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}else{
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return RESET;
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}
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}
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/*!
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\brief clear RTC interrupt flag status
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\param[in] flag: specify which flag status to clear
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one or more parameters can be selected which are shown as below:
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\arg RTC_INT_FLAG_SECOND: second interrupt flag
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\arg RTC_INT_FLAG_ALARM: alarm interrupt flag
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\arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag
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\param[out] none
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\retval none
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*/
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void rtc_interrupt_flag_clear(uint32_t flag)
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{
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/* clear RTC interrupt flag */
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RTC_CTL &= ~flag;
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}
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/*!
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\brief enable RTC interrupt
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\param[in] interrupt: specify which interrupt to enbale
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one or more parameters can be selected which are shown as below:
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\arg RTC_INT_SECOND: second interrupt
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\arg RTC_INT_ALARM: alarm interrupt
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\arg RTC_INT_OVERFLOW: overflow interrupt
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\param[out] none
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\retval none
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*/
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void rtc_interrupt_enable(uint32_t interrupt)
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{
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RTC_INTEN |= interrupt;
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}
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/*!
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\brief disable RTC interrupt
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\param[in] interrupt: specify which interrupt to disbale
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one or more parameters can be selected which are shown as below:
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\arg RTC_INT_SECOND: second interrupt
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\arg RTC_INT_ALARM: alarm interrupt
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\arg RTC_INT_OVERFLOW: overflow interrupt
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\param[out] none
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\retval none
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*/
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void rtc_interrupt_disable(uint32_t interrupt)
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{
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RTC_INTEN &= ~interrupt;
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}
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#define RTE_DEVICE_STDPERIPHERALS_PMU
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#define RTE_DEVICE_STDPERIPHERALS_PMU
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/* GigaDevice::Device:GD32F10x_StdPeripherals:RCU:2.0.2 */
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/* GigaDevice::Device:GD32F10x_StdPeripherals:RCU:2.0.2 */
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#define RTE_DEVICE_STDPERIPHERALS_RCU
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#define RTE_DEVICE_STDPERIPHERALS_RCU
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/* GigaDevice::Device:GD32F10x_StdPeripherals:RTC:2.0.2 */
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#define RTE_DEVICE_STDPERIPHERALS_RTC
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/* GigaDevice::Device:GD32F10x_StdPeripherals:USART:2.0.2 */
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/* GigaDevice::Device:GD32F10x_StdPeripherals:USART:2.0.2 */
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#define RTE_DEVICE_STDPERIPHERALS_USART
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#define RTE_DEVICE_STDPERIPHERALS_USART
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/* Keil.ARM Compiler::Compiler:I/O:STDIN:User:1.2.0 */
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/* Keil.ARM Compiler::Compiler:I/O:STDIN:User:1.2.0 */
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File diff suppressed because one or more lines are too long
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@ -153,7 +153,40 @@
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<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL040000 -FP0($$Device:GD32F107VC$Flash\GD32F10x_CL.FLM))</Name>
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<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL040000 -FP0($$Device:GD32F107VC$Flash\GD32F10x_CL.FLM))</Name>
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</SetRegEntry>
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</SetRegEntry>
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</TargetDriverDllRegistry>
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</TargetDriverDllRegistry>
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<Breakpoint/>
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<Breakpoint>
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<Bp>
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<Number>0</Number>
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<Type>0</Type>
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<LineNumber>287</LineNumber>
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<EnabledFlag>1</EnabledFlag>
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<Address>0</Address>
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<ByteObject>0</ByteObject>
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<HtxType>0</HtxType>
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<ManyObjects>0</ManyObjects>
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<SizeOfObject>0</SizeOfObject>
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<BreakByAccess>0</BreakByAccess>
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<BreakIfRCount>0</BreakIfRCount>
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<Filename>.\main.c</Filename>
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<ExecCommand></ExecCommand>
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<Expression></Expression>
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</Bp>
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<Bp>
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<Number>1</Number>
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<Type>0</Type>
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<LineNumber>286</LineNumber>
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<EnabledFlag>1</EnabledFlag>
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<Address>0</Address>
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<ByteObject>0</ByteObject>
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<HtxType>0</HtxType>
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<ManyObjects>0</ManyObjects>
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<SizeOfObject>0</SizeOfObject>
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<BreakByAccess>0</BreakByAccess>
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<BreakIfRCount>0</BreakIfRCount>
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<Filename>.\main.c</Filename>
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<ExecCommand></ExecCommand>
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<Expression></Expression>
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</Bp>
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</Breakpoint>
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<WatchWindow1>
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<WatchWindow1>
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<Ww>
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<Ww>
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<count>0</count>
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<count>0</count>
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</Mm>
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</Mm>
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</MemoryWindow3>
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</MemoryWindow3>
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<ScvdPack>
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<ScvdPack>
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<Filename>E:\Arm\Packs\ARM\CMSIS-FreeRTOS\10.5.1\CMSIS\RTOS2\FreeRTOS\FreeRTOS.scvd</Filename>
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<Filename>C:\Users\User\AppData\Local\Arm\Packs\ARM\CMSIS-FreeRTOS\10.5.1\CMSIS\RTOS2\FreeRTOS\FreeRTOS.scvd</Filename>
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<Type>ARM.CMSIS-FreeRTOS.10.5.1</Type>
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<Type>ARM.CMSIS-FreeRTOS.10.5.1</Type>
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<SubType>1</SubType>
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<SubType>1</SubType>
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</ScvdPack>
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</ScvdPack>
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<Group>
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<Group>
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<GroupName>FreeRTOS</GroupName>
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<GroupName>FreeRTOS</GroupName>
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<tvExp>1</tvExp>
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<tvExp>0</tvExp>
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<tvExpOptDlg>0</tvExpOptDlg>
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<tvExpOptDlg>0</tvExpOptDlg>
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<cbSel>0</cbSel>
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<cbSel>0</cbSel>
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<RteFlg>0</RteFlg>
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<RteFlg>0</RteFlg>
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<targetInfo name="Target 1"/>
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<targetInfo name="Target 1"/>
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</targetInfos>
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</targetInfos>
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</component>
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</component>
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<component Cclass="Device" Cgroup="GD32F10x_StdPeripherals" Csub="RTC" Cvendor="GigaDevice" Cversion="2.0.2" condition="GD32F10x STDPERIPHERALS RCU">
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<package name="GD32F10x_DFP" schemaVersion="1.2" url="https://gd32mcu.com/data/documents/pack/" vendor="GigaDevice" version="2.0.3"/>
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<targetInfos>
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<targetInfo name="Target 1"/>
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</targetInfos>
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</component>
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<component Cclass="Device" Cgroup="GD32F10x_StdPeripherals" Csub="USART" Cvendor="GigaDevice" Cversion="2.0.2" condition="GD32F10x STDPERIPHERALS RCU">
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<component Cclass="Device" Cgroup="GD32F10x_StdPeripherals" Csub="USART" Cvendor="GigaDevice" Cversion="2.0.2" condition="GD32F10x STDPERIPHERALS RCU">
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<package name="GD32F10x_DFP" schemaVersion="1.2" url="https://gd32mcu.com/data/documents/pack/" vendor="GigaDevice" version="2.0.3"/>
|
<package name="GD32F10x_DFP" schemaVersion="1.2" url="https://gd32mcu.com/data/documents/pack/" vendor="GigaDevice" version="2.0.3"/>
|
||||||
<targetInfos>
|
<targetInfos>
|
||||||
|
|
@ -959,6 +965,14 @@
|
||||||
<targetInfo name="Target 1"/>
|
<targetInfo name="Target 1"/>
|
||||||
</targetInfos>
|
</targetInfos>
|
||||||
</file>
|
</file>
|
||||||
|
<file attr="config" category="source" name="Device\Firmware\Peripherals\src\gd32f10x_rtc.c" version="2.0.2">
|
||||||
|
<instance index="0">RTE\Device\GD32F107VC\gd32f10x_rtc.c</instance>
|
||||||
|
<component Cclass="Device" Cgroup="GD32F10x_StdPeripherals" Csub="RTC" Cvendor="GigaDevice" Cversion="2.0.2" condition="GD32F10x STDPERIPHERALS RCU"/>
|
||||||
|
<package name="GD32F10x_DFP" schemaVersion="1.2" url="https://gd32mcu.com/data/documents/pack/" vendor="GigaDevice" version="2.0.3"/>
|
||||||
|
<targetInfos>
|
||||||
|
<targetInfo name="Target 1"/>
|
||||||
|
</targetInfos>
|
||||||
|
</file>
|
||||||
<file attr="config" category="source" name="Device\Firmware\Peripherals\src\gd32f10x_usart.c" version="2.0.2">
|
<file attr="config" category="source" name="Device\Firmware\Peripherals\src\gd32f10x_usart.c" version="2.0.2">
|
||||||
<instance index="0">RTE\Device\GD32F107VC\gd32f10x_usart.c</instance>
|
<instance index="0">RTE\Device\GD32F107VC\gd32f10x_usart.c</instance>
|
||||||
<component Cclass="Device" Cgroup="GD32F10x_StdPeripherals" Csub="USART" Cvendor="GigaDevice" Cversion="2.0.2" condition="GD32F10x STDPERIPHERALS RCU"/>
|
<component Cclass="Device" Cgroup="GD32F10x_StdPeripherals" Csub="USART" Cvendor="GigaDevice" Cversion="2.0.2" condition="GD32F10x STDPERIPHERALS RCU"/>
|
||||||
|
|
|
||||||
27
main.c
27
main.c
|
|
@ -190,8 +190,18 @@ static void vInitMCU(void)
|
||||||
rcu_periph_clock_enable(RCU_ENET);
|
rcu_periph_clock_enable(RCU_ENET);
|
||||||
rcu_periph_clock_enable(RCU_ENETTX);
|
rcu_periph_clock_enable(RCU_ENETTX);
|
||||||
rcu_periph_clock_enable(RCU_ENETRX);
|
rcu_periph_clock_enable(RCU_ENETRX);
|
||||||
|
rcu_periph_clock_enable(RCU_RTC);
|
||||||
|
rcu_rtc_clock_config(RCU_RTCSRC_LXTAL);
|
||||||
|
|
||||||
/*Configure GPIO Alternate UART function*/
|
/* Configure RTC */
|
||||||
|
|
||||||
|
rtc_configuration_mode_enter();
|
||||||
|
rtc_lwoff_wait();
|
||||||
|
rtc_counter_set(0xA5A5A5A5);
|
||||||
|
//rtc_lwoff_wait();
|
||||||
|
rtc_configuration_mode_exit();
|
||||||
|
|
||||||
|
/* Configure GPIO Alternate UART function */
|
||||||
gd_eval_com_init(EVAL_COM1);
|
gd_eval_com_init(EVAL_COM1);
|
||||||
gpio_init(GPIOB, GPIO_MODE_IPU, GPIO_OSPEED_2MHZ, BUTTON_USER);
|
gpio_init(GPIOB, GPIO_MODE_IPU, GPIO_OSPEED_2MHZ, BUTTON_USER);
|
||||||
|
|
||||||
|
|
@ -201,7 +211,7 @@ static void vInitMCU(void)
|
||||||
gpio_init(LED5_TICK_PORT, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, LED5_TICK);
|
gpio_init(LED5_TICK_PORT, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, LED5_TICK);
|
||||||
gpio_bit_set(LED5_TICK_PORT, LED5_TICK);
|
gpio_bit_set(LED5_TICK_PORT, LED5_TICK);
|
||||||
|
|
||||||
/*Enable PLL2 to generate 50MHz clocks */
|
/* Enable PLL2 to generate 50MHz clocks */
|
||||||
if (ERROR == xInitPLL2()) FreeRTOS_debug_printf(("PLL2 initialization failed\n"));
|
if (ERROR == xInitPLL2()) FreeRTOS_debug_printf(("PLL2 initialization failed\n"));
|
||||||
|
|
||||||
/* Put PLL2 clocks into CKOUT0(PA1) as ref clock for ethernet phy */
|
/* Put PLL2 clocks into CKOUT0(PA1) as ref clock for ethernet phy */
|
||||||
|
|
@ -209,7 +219,7 @@ static void vInitMCU(void)
|
||||||
gpio_ethernet_phy_select(GPIO_ENET_PHY_RMII);
|
gpio_ethernet_phy_select(GPIO_ENET_PHY_RMII);
|
||||||
|
|
||||||
/* Configure GPIO Alternate RMII function */
|
/* Configure GPIO Alternate RMII function */
|
||||||
gpio_init(RMII_TXD_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, RMII_TX_EN);
|
gpio_init(RMII_TXD_PORT, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, RMII_TX_EN);
|
||||||
gpio_init(RMII_TXD_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, RMII_TXD0);
|
gpio_init(RMII_TXD_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, RMII_TXD0);
|
||||||
gpio_init(RMII_TXD_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, RMII_TXD1);
|
gpio_init(RMII_TXD_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, RMII_TXD1);
|
||||||
|
|
||||||
|
|
@ -269,14 +279,13 @@ void vTaskToggleLed( void *pvParameters)
|
||||||
|
|
||||||
static void prvMiscInitialisation( void )
|
static void prvMiscInitialisation( void )
|
||||||
{
|
{
|
||||||
unsigned long xTimeNow;
|
UBaseType_t xTimeNow;
|
||||||
uint32_t ulRandomNumbers[ 4 ];
|
uint32_t ulRandomNumbers[ 4 ];
|
||||||
|
|
||||||
/* Seed the random number generator. */
|
/* Seed the random number generator. */
|
||||||
// time( &xTimeNow );
|
xTimeNow = rtc_counter_get();
|
||||||
FreeRTOS_debug_printf( ("Seed for randomiser: %lu\r\n", xTimeNow ) );
|
FreeRTOS_debug_printf( ("Seed for randomiser: %lu\r\n", xTimeNow ) );
|
||||||
FreeRTOS_debug_printf( ("Seed for randomiser\n") );
|
prvSRand( ( uint32_t ) xTimeNow );
|
||||||
// prvSRand( ( uint32_t ) xTimeNow );
|
|
||||||
|
|
||||||
( void ) xApplicationGetRandomNumber( &ulRandomNumbers[ 0 ] );
|
( void ) xApplicationGetRandomNumber( &ulRandomNumbers[ 0 ] );
|
||||||
( void ) xApplicationGetRandomNumber( &ulRandomNumbers[ 1 ] );
|
( void ) xApplicationGetRandomNumber( &ulRandomNumbers[ 1 ] );
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue